 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 21.2-S3-C2410X-052003 USER'S MANUAL S3C2410X 32-Bit RISC Microprocessor Revision 1.2 S3C2410X 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1.2 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. S3C2410X 32-Bit RISC Microprocessor User's Manual, Revision 1.2 Publication Number: 21.2-S3-C2410X-052003 (c) 2003 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-9001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung- Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(031)-209-1934 FAX: (82)-(031)-209-1899 Home Page: http://www.samsungsemi.com Printed in the Republic of Korea "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. Table of Contents Chapter 1 Product Overview Introduction..............................................................................................................................................1-1 Features ..................................................................................................................................................1-2 Block Diagram .........................................................................................................................................1-5 Pin Assignments ......................................................................................................................................1-6 Signal Descriptions..........................................................................................................................1-20 S3C2410X Special Registers...........................................................................................................1-25 Chapter 2 Programmer's Model Overview .................................................................................................................................................2-1 Processor Operating States.............................................................................................................2-1 Switching State ...............................................................................................................................2-1 Memory Formats .............................................................................................................................2-1 Big-Endian Format ..........................................................................................................................2-2 Little-Endian Format........................................................................................................................2-2 Instruction Length............................................................................................................................2-2 Operating Modes.............................................................................................................................2-3 Registers .........................................................................................................................................2-3 The Program Status Registers.........................................................................................................2-7 Exceptions ......................................................................................................................................2-10 Interrupt Latencies...........................................................................................................................2-15 Reset...............................................................................................................................................2-15 S3C2410X MICROPROCESSOR iii Table of Contents (Continued) Chapter 3 ARM Instruction Set Instruction Set Summay.......................................................................................................................... 3-1 Format Summary ........................................................................................................................... 3-1 Instruction Summary....................................................................................................................... 3-2 The Condition Field................................................................................................................................. 3-4 Branch and Exchange (BX)..................................................................................................................... 3-5 Instruction Cycle Times .................................................................................................................. 3-5 Assembler Syntax........................................................................................................................... 3-5 Using R15 As An Operand.............................................................................................................. 3-5 Branch and Branch With Link (B, BL)...................................................................................................... 3-7 The Link Bit .................................................................................................................................... 3-7 Instruction Cycle Times .................................................................................................................. 3-7 Assembler Syntax........................................................................................................................... 3-8 Data Processing...................................................................................................................................... 3-9 Cpsr Flags ...................................................................................................................................... 3-11 Shifts.............................................................................................................................................. 3-12 Immediate Operand Rotates........................................................................................................... 3-16 Writing to R15 ................................................................................................................................ 3-16 Using R15 As an Operandy ............................................................................................................ 3-16 TEQ, TST, CMP and CMN Opcodes............................................................................................... 3-16 Instruction Cycle Times .................................................................................................................. 3-16 Assembler Syntax........................................................................................................................... 3-17 Examples ....................................................................................................................................... 3-17 PSR Transfer (MRS, MSR) ..................................................................................................................... 3-18 Operand Restrictions ...................................................................................................................... 3-18 Reserved Bits ................................................................................................................................. 3-20 Examples ....................................................................................................................................... 3-20 Instruction Cycle Times .................................................................................................................. 3-20 Assembly Syntax............................................................................................................................ 3-21 Examples ....................................................................................................................................... 3-21 Multiply and Multiply-Accumulate (MUL, MLA) ........................................................................................ 3-22 CPSR Flags.................................................................................................................................... 3-24 Instruction Cycle Times .................................................................................................................. 3-24 Assembler Syntax........................................................................................................................... 3-24 Examples ....................................................................................................................................... 3-24 Multiply Long and Multiply-Accumulate Long (MULL, MLAL)................................................................... 3-25 Operand Restrictions ...................................................................................................................... 3-26 Cpsr Flags ...................................................................................................................................... 3-26 Instruction Cycle Times .................................................................................................................. 3-26 Assembler Syntax........................................................................................................................... 3-27 Examples ....................................................................................................................................... 3-27 iv S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 3 ARM Instruction Set (Continued) Single Data Transfer (LDR, STR).............................................................................................................3-28 Offsets and Auto-Indexing ...............................................................................................................3-29 Shifted Register Offset ....................................................................................................................3-29 Bytes and Words .............................................................................................................................3-29 Use Of R15 .....................................................................................................................................3-31 Example:.........................................................................................................................................3-31 Data Aborts .....................................................................................................................................3-31 Instruction Cycle Times ...................................................................................................................3-31 Assembler Syntax ...........................................................................................................................3-32 Examples ........................................................................................................................................3-33 Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH).........................................................3-34 Offsets and Auto-Indexing ...............................................................................................................3-35 Halfword Load And Stores ...............................................................................................................3-36 Use of R15 ......................................................................................................................................3-37 Data Aborts .....................................................................................................................................3-37 Instruction Cycle Times ...................................................................................................................3-37 Assembler Syntax ...........................................................................................................................3-38 Examples ........................................................................................................................................3-39 Block Data Transfer (LDM, STM).............................................................................................................3-40 The Register List .............................................................................................................................3-40 Addressing Modes ...........................................................................................................................3-41 Address Alignment ..........................................................................................................................3-41 Use of the S Bit ...............................................................................................................................3-43 Use of R15 as the Base...................................................................................................................3-43 Inclusion of the Base In the Register List .........................................................................................3-44 Data Aborts .....................................................................................................................................3-44 Instruction Cycle Times ...................................................................................................................3-44 Assembler Syntax ...........................................................................................................................3-45 Examples ........................................................................................................................................3-46 Single Data Swap (SWP).........................................................................................................................3-47 Bytes and Words .............................................................................................................................3-47 Use of R15 ......................................................................................................................................3-48 Data Aborts .....................................................................................................................................3-48 Instruction Cycle Times ...................................................................................................................3-48 Assembler Syntax ...........................................................................................................................3-48 Software Interrupt (SWI) ..........................................................................................................................3-49 Return from the Supervisor .............................................................................................................3-49 Comment Field................................................................................................................................3-49 Instruction Cycle Times ...................................................................................................................3-49 Assembler Syntax ...........................................................................................................................3-50 Coprocessor Data Operations (CDP) .......................................................................................................3-51 Coprocessor Instructions .................................................................................................................3-51 Instruction Cycle Times ...................................................................................................................3-52 Examples ........................................................................................................................................3-52 S3C2410X MICROPROCESSOR v Table of Contents (Continued) Chapter 3 ARM Instruction Set (Continued) Coprocessor Data Transfers (LDC, STC) ................................................................................................ 3-53 The Coprocessor Fields.................................................................................................................. 3-54 Addressing Modes .......................................................................................................................... 3-54 Address Alignment ......................................................................................................................... 3-54 Data Aborts .................................................................................................................................... 3-54 Assembler Syntax........................................................................................................................... 3-55 Examples ....................................................................................................................................... 3-55 Coprocessor Register Transfers (MRC, MCR) ................................................................................ 3-56 The Coprocessor Fields.................................................................................................................. 3-56 Transfers to R15............................................................................................................................. 3-57 Transfers from R15......................................................................................................................... 3-57 Instruction Cycle Times .................................................................................................................. 3-57 Assembler Syntax........................................................................................................................... 3-57 Examples ....................................................................................................................................... 3-57 Undefined Instruction...................................................................................................................... 3-58 Instruction Cycle Times .................................................................................................................. 3-58 Assembler Syntax........................................................................................................................... 3-58 Instruction Set Examples ................................................................................................................ 3-59 Using The Conditional Instructions.................................................................................................. 3-59 Pseudo-Random Binary Sequence Generator................................................................................. 3-61 Multiplication by Constant Using the Barrel Shifter.......................................................................... 3-61 Loading a Word from an Unknown Alignment ................................................................................. 3-63 Chapter 4 THUMB Instruction Set THUMB Instruction Set Format ............................................................................................................... 4-1 Format Summary ........................................................................................................................... 4-2 Opcode Summary .......................................................................................................................... 4-3 Format 1: Move Shifted Register ............................................................................................................ 4-5 Operation ....................................................................................................................................... 4-5 Instruction Cycle Times .................................................................................................................. 4-6 Examples ....................................................................................................................................... 4-6 Format 2: Add/Subtract........................................................................................................................... 4-7 Operation ....................................................................................................................................... 4-7 Instruction Cycle Times .................................................................................................................. 4-8 Examples ....................................................................................................................................... 4-8 Format 3: Move/Compare/Add/Subtract Immediate ................................................................................ 4-9 Operations...................................................................................................................................... 4-9 Instruction Cycle Times .................................................................................................................. 4-10 Examples ....................................................................................................................................... 4-10 Format 4: ALU Operations ...................................................................................................................... 4-11 Operation ....................................................................................................................................... 4-11 Instruction Cycle Times .................................................................................................................. 4-12 Examples ....................................................................................................................................... 4-12 vi S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 4 THUMB Instruction Set (Continued) Format 5: Hi-Register Operations/Branch Exchange................................................................................4-13 Operation ........................................................................................................................................4-13 Instruction Cycle Times ...................................................................................................................4-14 The Bx Instruction ...........................................................................................................................4-14 Examples ........................................................................................................................................4-15 Using R15 As An Operand...............................................................................................................4-15 Format 6: Pc-Relative Load .....................................................................................................................4-16 Operation ........................................................................................................................................4-16 Instruction Cycle Times ...................................................................................................................4-17 Examples ........................................................................................................................................4-17 Format 7: Load/Store With Register Offset ..............................................................................................4-18 Operation ........................................................................................................................................4-19 Instruction Cycle Times ...................................................................................................................4-19 Examples ........................................................................................................................................4-19 Format 8: Load/Store Sign-Extended Byte/Halfword ................................................................................4-20 Operation ........................................................................................................................................4-20 Instruction Cycle Times ...................................................................................................................4-21 Examples ........................................................................................................................................4-21 Format 9: Load/Store With Immediate Offset...........................................................................................4-22 Operation ........................................................................................................................................4-23 Instruction Cycle Times ...................................................................................................................4-23 Examples ........................................................................................................................................4-23 Format 10: Load/Store Halfword ..............................................................................................................4-24 Operation ........................................................................................................................................4-24 Examples ........................................................................................................................................4-25 Format 11: Sp-Relative Load/Store..........................................................................................................4-26 Operation ........................................................................................................................................4-26 Instruction Cycle Times ...................................................................................................................4-27 Examples ........................................................................................................................................4-27 Format 12: Load Address.........................................................................................................................4-28 Operation ........................................................................................................................................4-28 Instruction Cycle Times ...................................................................................................................4-29 Examples ........................................................................................................................................4-29 Format 13: Add Offset To Stack Pointer ..................................................................................................4-30 Operation ........................................................................................................................................4-30 Instruction Cycle Times ...................................................................................................................4-30 Examples ........................................................................................................................................4-30 Format 14: Push/Pop Registers ...............................................................................................................4-31 Operation ........................................................................................................................................4-31 Instruction Cycle Times ...................................................................................................................4-32 Examples ........................................................................................................................................4-32 Format 15: Multiple Load/Store................................................................................................................4-33 Operation ........................................................................................................................................4-33 Instruction Cycle Times ...................................................................................................................4-33 Examples ........................................................................................................................................4-33 S3C2410X MICROPROCESSOR vii Table of Contents (Continued) Chapter 4 THUMB Instruction Set (Continued) Format 16: Conditional Branch................................................................................................................ 4-34 Operation ....................................................................................................................................... 4-34 Instruction Cycle Times .................................................................................................................. 4-35 Examples ....................................................................................................................................... 4-35 Operation ....................................................................................................................................... 4-36 Instruction Cycle Times .................................................................................................................. 4-36 Examples ....................................................................................................................................... 4-36 Format 18: Unconditional Branch............................................................................................................ 4-37 Operation ....................................................................................................................................... 4-37 Examples ....................................................................................................................................... 4-37 Operation ....................................................................................................................................... 4-38 Instruction Cycle Times .................................................................................................................. 4-39 Examples ....................................................................................................................................... 4-39 Instruction Set Examples ........................................................................................................................ 4-40 Multiplication By a Constant Using Shifts and Adds ........................................................................ 4-40 General Purpose Signed Divide...................................................................................................... 4-41 Division by a Constant.................................................................................................................... 4-43 Chapter 5 Memory Controller Overview ................................................................................................................................................ 5-1 Function Description ............................................................................................................................... 5-3 Bank0 Bus Width............................................................................................................................ 5-3 Memory (SROM/SDRAM) Address Pin Connections....................................................................... 5-3 Sdram Bank Address Pin Connection ............................................................................................. 5-4 Nwait Pin Operation........................................................................................................................ 5-5 nXBREQ/nXBACK Pin Operation.................................................................................................... 5-6 Programmable Access Cycle.......................................................................................................... 5-11 Bus Width & Wait Control Register (BWSCON).............................................................................. 5-13 Bank Control Register (BANKCONN: nGCS0-nGCS5).................................................................... 5-15 Bank Control Register (BANKCONn: nGCS6-nGCS7) .................................................................... 5-16 Refresh Control Register ................................................................................................................ 5-17 Banksize Register........................................................................................................................... 5-18 SDRAM Mode Register Set Register (MRSR)................................................................................. 5-19 viii S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 6 NAND Flash Controller Overview .................................................................................................................................................6-1 Features..........................................................................................................................................6-1 Block Diagram.................................................................................................................................6-2 Operation Scheme ..........................................................................................................................6-2 Auto Boot Mode Sequence ..............................................................................................................6-3 Nand Flash Mode Configuration ......................................................................................................6-3 Nand Flash Memory Timing ............................................................................................................6-3 Pin Configuration.............................................................................................................................6-4 Boot and Nand Flash Configurations ...............................................................................................6-4 512-Byte ECC Parity Code Assignment Table .................................................................................6-4 Special Function Registers ......................................................................................................................6-6 Nand Flash Configuration (NFCONF) Register ................................................................................6-6 Nand Flash Command Set (NFCMD) Register.................................................................................6-7 Nand Flash Address Set (NFADDR) Register ..................................................................................6-7 Nand Flash Data (NFDATA) Register ..............................................................................................6-7 Nand Flash Operation Status (NFSTAT) Register............................................................................6-8 Nand Flash ECC (NFECC) Register ................................................................................................6-8 Chapter 7 Clock & Power Management Overview .................................................................................................................................................7-1 Functional Description .............................................................................................................................7-2 Clock Architecture ...........................................................................................................................7-2 Clock Source Selection ...................................................................................................................7-2 Phase Locked Loop (PLL) ...............................................................................................................7-4 Clock Control Logic .........................................................................................................................7-6 Power Management ........................................................................................................................7-9 Clock Generator & Power Management Special Register.........................................................................7-19 Lock Time Count Register (LOCKTIME)..........................................................................................7-19 PLL Value Selection Table ..............................................................................................................7-20 Clock Control Register (CLKCON)...................................................................................................7-21 Clock Slow Control (CLKSLOW) Register........................................................................................7-22 Clock Divider Control (CLKDIVN) Register ......................................................................................7-22 S3C2410X MICROPROCESSOR ix Table of Contents (Continued) Chapter 8 DMA Overview ................................................................................................................................................ 8-1 DMA Request Sources............................................................................................................................ 8-2 DMA Operation ....................................................................................................................................... 8-2 Examples ....................................................................................................................................... 8-6 DMA Special Registers ........................................................................................................................... 8-7 DMA Initial Source (DISRC) Register.............................................................................................. 8-7 DMA Initial Source Control (DISRCC) Register............................................................................... 8-7 DMA Initial Destination (DIDST) Register ....................................................................................... 8-8 DMA Initial Destination Control (DIDSTC) Register......................................................................... 8-8 DMA Control (DCON) Register ....................................................................................................... 8-9 DMA Status (DSTAT) Register ....................................................................................................... 8-11 DMA Current Source (DCSRC) Register......................................................................................... 8-11 Current Destination (DCDST) Register ........................................................................................... 8-12 DMA Mask Trigger (DMASKTRIG) Register.................................................................................... 8-13 Chapter 9 I/O ports Overview ................................................................................................................................................ 9-1 Port Control Descriptions ........................................................................................................................ 9-7 Port Configuration Register (GPACON-GPHCON).......................................................................... 9-7 Port Data Register (GPADAT-GPHDAT)......................................................................................... 9-7 Port Pull-Up Register (GPBUP-GPHUP)......................................................................................... 9-7 Miscellaneous Control Register....................................................................................................... 9-7 External Interrupt Control Register (EXTINTN) ............................................................................... 9-7 Power_Off Mode and I/O Ports....................................................................................................... 9-7 I/O Port Control Register......................................................................................................................... 9-8 Port A Control Registers (GPACON/GPADAT) ............................................................................... 9-8 Port B Control Registers (GPBCON, GPBDAT, and GPBUP) ......................................................... 9-9 Port C Control Registers (GPCCON, GPCDAT, and GPCUP)......................................................... 9-10 Port D Control Registers (GPDCON, GPDDAT, and GPDUP)......................................................... 9-12 Port E Control Registers (GPECON, GPEDAT, and GPEUP) ......................................................... 9-14 Port F Control Registers (GPFCON, GPFDAT, and GPFPU).......................................................... 9-16 Port G Control Registers (GPGCON, GPGDAT, AND GPGUP) ...................................................... 9-17 Port H Control Registers (GPHCON, GPHDAT, AND GPHUP) ....................................................... 9-19 Miscellaneous Control Register (MISCCR) ..................................................................................... 9-20 DCLK Control Registers (DCLKCON) ............................................................................................. 9-21 External Interrupt Control Register (EXTINTn) ................................................................................ 9-22 External Interrupt Filter Register (EINTFLTn) ................................................................................. 9-25 External Interrupt Mask Register (EINTMASK) ............................................................................... 9-26 External Interrupt Pending Register (EINTPENDn) ........................................................................ 9-27 General Status Register (GSTATUSn)............................................................................................ 9-28 x S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 10 PWM Timer Overview .................................................................................................................................................10-1 PWM Timer Operation.............................................................................................................................10-3 Prescaler & Divider .........................................................................................................................10-3 Auto Reload & Double Buffering......................................................................................................10-4 Timer Initialization Using Manual Update Bit and Inverter Bit ..........................................................10-5 Timer Operation ..............................................................................................................................10-6 Pulse Width Modulation (PWM).......................................................................................................10-7 Output Level Control .......................................................................................................................10-8 Dead Zone Generator......................................................................................................................10-9 Dma Request Mode.........................................................................................................................10-10 PWM Timer Control Registers .................................................................................................................10-11 Timer Configuration Register0 (TCFG0) ..........................................................................................10-11 Timer Configuration Register1 (TCFG1) ..........................................................................................10-12 Timer Control (TCON) Register .......................................................................................................10-13 Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)..............................10-15 Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)..............................10-16 Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)..............................10-17 Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)..............................10-18 Timer 3 Count Observation Register (TCNTO3) ..............................................................................10-18 Timer 4 Count Buffer Register (TCNTB4) ........................................................................................10-19 Chapter 11 UART Overview .................................................................................................................................................11-1 Features..........................................................................................................................................11-1 Block Diagram .........................................................................................................................................11-2 UART Operation..............................................................................................................................11-3 UART Special Registers ..........................................................................................................................11-10 UART Line Control Register ............................................................................................................11-10 UART Control Register....................................................................................................................11-11 UART FIFO Control Register...........................................................................................................11-13 UART Modem Control Register .......................................................................................................11-14 UART Tx/Rx Status Register ...........................................................................................................11-15 UART Error Status Register.............................................................................................................11-16 UART FIFO Status Register ............................................................................................................11-17 UART Modem Status Register.........................................................................................................11-18 UART Transmit Buffer Register (Holding Register & FIFO Register)................................................11-19 UART Receive Buffer Register (Holding Register & FIFO Register) ................................................11-19 UART Baud Rate Divisor Register...................................................................................................11-20 S3C2410X MICROPROCESSOR xi Table of Contents (Continued) Chapter 12 USB Host Controller Overview ................................................................................................................................................ 12-1 USB Host Controller Special Registers ........................................................................................... 12-2 Chapter 13 USB Device Overview ................................................................................................................................................ 13-1 Feature........................................................................................................................................... 13-1 USB Device Controller Special Registers................................................................................................ 13-3 Function Address Register (FUNC_ADDR_REG)............................................................................ 13-5 Power Management Register (PWR_REG)..................................................................................... 13-6 Interrupt Register (EP_INT_REG/USB_INT_REG) ......................................................................... 13-7 Interrupt Enable Register (EP_INT_EN_REG/USB_INT_REG)....................................................... 13-9 Frame Number Register (FPAME_NUM1_REG/FRAME_NUM2_REG) .......................................... 13-10 Index Register (INDEX_REG)......................................................................................................... 13-11 END Point0 Control Status Register (EP0_CSR) ............................................................................ 13-12 END Point In Control Status Register (IN_CSR1_REG/IN_CSR2_REG)......................................... 13-14 END Point Out Control Status Register (OUT_CSR1_REG/OUT_CSR2_REG) .............................. 13-16 END Point FIFO Register (EPN_FIFO_REG) ................................................................................. 13-18 MAX Packet Register (MAXP_REG) ............................................................................................... 13-19 END Point Out Write Count Register (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) .............. 13-20 DMA Interface Control Register (EPN_DMA_CON) ........................................................................ 13-21 DMA Unit Counter Register (EPN_DMA_UNIT) .............................................................................. 13-22 DMA FIFO Counter Register (EPN_DMA_FIFO) ............................................................................ 13-23 DMA Total Transfer Counter Register (EPN_DMA_TTC_L,M,H)..................................................... 13-24 xii S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 14 Interrupt Controller Overview .................................................................................................................................................14-1 Interrupt Controller Operation ..........................................................................................................14-2 Interrupt Sources.............................................................................................................................14-3 Interrupt Priority Generating Block...................................................................................................14-4 Interrupt Priority...............................................................................................................................14-5 Interrupt Controller Special Registers.......................................................................................................14-6 Source Pending (Srcpnd) Register...................................................................................................14-6 Interrupt Mode (INTMOD) Register..................................................................................................14-8 Interrupt Mask (INTMSK) Register...................................................................................................14-10 Priority Register (PRIORITY)...........................................................................................................14-12 Interrupt Pending (INTPND) Register...............................................................................................14-14 Interrupt Offset (INTOFFSET) Register ...........................................................................................14-16 SUB Source Pending (SUBSRCPND) Register................................................................................14-17 Interrupt Sub Mask (INTSUBMSK) Register ....................................................................................14-18 Chapter 15 LCD Controller Overview .................................................................................................................................................15-1 Features..........................................................................................................................................15-1 Common Features...........................................................................................................................15-2 External Interface Signal .................................................................................................................15-2 Block Diagram.................................................................................................................................15-3 STN LCD Controller Operation ................................................................................................................15-4 Timing Generator (TIMEGEN).........................................................................................................15-4 Video Operation ..............................................................................................................................15-5 Dithering and Frame Rate Control ...................................................................................................15-7 Memory Data Format (STN, BSWP=0)............................................................................................15-9 TFT LCD Controller Operation .................................................................................................................15-15 Video Operation ..............................................................................................................................15-15 Memory Data Format (TFT).............................................................................................................15-16 256 Palette Usage (TFT) .................................................................................................................15-20 Samsung TFT LCD Panel (3.5 Portrait / 256k Color /Reflective A-SI TFT LCD) .............................15-23 Virtual Display (TFT/STN) ...............................................................................................................15-24 LCD Power Enable (STN/TFT) ........................................................................................................15-25 LCD Controller Special Registers ....................................................................................................15-26 Frame Buffer Start Address 1 Register ............................................................................................15-32 S3C2410X MICROPROCESSOR xiii Table of Contents (Continued) Chapter 16 A/D Converter Overview ................................................................................................................................................ 16-1 Features ......................................................................................................................................... 16-1 ADC & Touch Screen Interface Operation............................................................................................... 16-2 Block Diagram................................................................................................................................ 16-2 Example for Touch Screen ............................................................................................................. 16-3 Function Descriptions ..................................................................................................................... 16-4 ADC and Touch Screen Interface Special Registers................................................................................ 16-7 ADC Control (ADCCON) Register................................................................................................... 16-7 ADC Touch Screen Control (ADCTSC) Register............................................................................. 16-8 ADC Start Delay (ADCDLY) Register.............................................................................................. 16-9 ADC Conversion Data (ADCDAT1) Register................................................................................... 16-11 Chapter 17 RTC (Real Time Clock) Overview ................................................................................................................................................ 17-1 Features ......................................................................................................................................... 17-1 Real Time Clock Operation............................................................................................................. 17-2 Leap Year Generator ...................................................................................................................... 17-2 Read/Write Registers ..................................................................................................................... 17-3 Backup Battery Operation............................................................................................................... 17-3 Alarm Function ............................................................................................................................... 17-3 Tick Time Interrupt ......................................................................................................................... 17-3 Round Reset Function .................................................................................................................... 17-3 32.768kHz X-Tal Connection Example .......................................................................................... 17-4 Real Time Clock Special Registers ......................................................................................................... 17-5 Real Time Clock Control (RTCCON) Register ................................................................................ 17-5 Tick Time Count (TICNT) Register ................................................................................................. 17-5 RTC Alarm Control (RTCALM) Register ......................................................................................... 17-6 Alarm Second Data (ALMSEC) Register......................................................................................... 17-7 Alarm Min Data (ALMMIN) Register................................................................................................ 17-7 Alarm Hour Data (ALMHOUR) Register .......................................................................................... 17-7 Alarm Date Data (ALMDATE) Register ........................................................................................... 17-8 Alarm Mon Data (ALMMON) Register............................................................................................. 17-8 Alarm Year Data (ALMYEAR) Register........................................................................................... 17-8 RTC Round Reset (RTCRST) Register ........................................................................................... 17-9 BCD Second (BCDSEC) Register................................................................................................... 17-9 BCD Minute (BCDMIN) Register..................................................................................................... 17-9 BCD Hour (BCDHOUR) Register .................................................................................................... 17-10 BCD Date (BCDDATE) Register ..................................................................................................... 17-10 BCD Day (BCDDAY) Register ........................................................................................................ 17-10 BCD Month (BCDMON) Register .................................................................................................... 17-11 BCD Year (BCDYEAR) Register ..................................................................................................... 17-11 xiv S3C2410X MICROPROCESSOR Table of Contents (Continued) Chapter 18 Watchdog Timer Overview .................................................................................................................................................18-1 Features..........................................................................................................................................18-1 Watchdog Timer Operation .............................................................................................................18-2 WTDAT & WTCNT..........................................................................................................................18-2 Consideration of Debugging Environment........................................................................................18-2 Watchdog Timer Special Registers..........................................................................................................18-3 Watchdog Timer Control (WTCON) Register...................................................................................18-3 Watchdog Timer Data (WTDAT) Register .......................................................................................18-4 Watchdog Timer Count (WTCNT) Register .....................................................................................18-4 Chapter 19 SDI Interface Overview .................................................................................................................................................19-1 Features..........................................................................................................................................19-1 Block Diagram.................................................................................................................................19-2 SDI Operation .................................................................................................................................19-3 SDIO Operation...............................................................................................................................19-4 SDI Special Registers......................................................................................................................19-5 Chapter 20 IIC-Bus Interface Overview .................................................................................................................................................20-1 The IIC-Bus Interface ......................................................................................................................20-3 Start and Stop Conditions................................................................................................................20-3 Data Transfer Format ......................................................................................................................20-4 ACK Signal Transmission ................................................................................................................20-5 Read-Write Operation .....................................................................................................................20-6 Bus Arbitration Procedures ..............................................................................................................20-6 Abort Conditions..............................................................................................................................20-6 Configuring the IIC-Bus ...................................................................................................................20-6 Flowcharts of the Operations in Each Mode.....................................................................................20-7 IIC-Bus Interface Special Registers..........................................................................................................20-11 Multi-Master IIC-Bus Control Register (IICCON) ..............................................................................20-11 Multi-Master IIC-Bus Address Register (IICADD) .............................................................................20-13 Multi-Master IIC-Bus Transmit/Receive Data Shift Register (IICDS) ................................................20-13 S3C2410X MICROPROCESSOR xv Table of Contents (Continued) Chapter 21 IIS-Bus Interface Overview ................................................................................................................................................ 21-1 Block Diagram ........................................................................................................................................ 21-2 Functional Descriptions........................................................................................................................... 21-2 Transmit or Receive only Mode ...................................................................................................... 21-2 Audio Serial Interface Format ................................................................................................................. 21-3 IIS-Bus Format ............................................................................................................................... 21-3 MSB (Left) Justified ........................................................................................................................ 21-3 Sampling Frequency and Master Clock........................................................................................... 21-4 IIS-Bus Interface Special Registers......................................................................................................... 21-5 IIS Control (IISCON) Register......................................................................................................... 21-5 IIS Mode Register (IISMOD) Register ............................................................................................. 21-6 IIS Prescaler (IISPSR) Register ...................................................................................................... 21-7 IIS FIFO Control (IISFCON) Register.............................................................................................. 21-8 IIS FIFO (IISFIFO) Register............................................................................................................ 21-8 Chapter 22 SPI Interface Overview ................................................................................................................................................ 22-1 Features ......................................................................................................................................... 22-1 Block Diagram................................................................................................................................ 22-2 SPI Operation................................................................................................................................. 22-3 SPI Special Registers ............................................................................................................................. 22-7 SPI Control Register....................................................................................................................... 22-7 SPI Status Register ........................................................................................................................ 22-8 SPI Pin Control Register................................................................................................................. 22-9 xvi S3C2410X MICROPROCESSOR Table of Contents (Concluded) Chapter 23 BUS PRIORITIES Overview .................................................................................................................................................23-1 Bus Priority Map..............................................................................................................................23-1 Chapter 24 Electrical Data Absolute Maximum Ratings .....................................................................................................................24-1 Recommended Operating Conditions ......................................................................................................24-1 D.C. Electrical Characteristics..................................................................................................................24-2 A.C. Electrical Characteristics..................................................................................................................24-5 Chapter 25 Mechanical Data Package Dimensions ...............................................................................................................................25-1 S3C2410X MICROPROCESSOR xvii List of Figures Figure Number 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 Title Page Number S3C2410X Block Diagram ......................................................................................1-5 S3C2410X Pin Assignments (272-FBGA) ...............................................................1-6 Big-Endian Addresses of Bytes within Words..........................................................2-2 Little-Endian Addresses of Bytes within Words .......................................................2-2 Register Organization in ARM State .......................................................................2-4 Register Organization in THUMB state ...................................................................2-5 Mapping of THUMB State Registers onto ARM State Registers..............................2-6 Program Status Register Format ............................................................................2-7 ARM Instruction Set Format ...................................................................................3-1 Branch and Exchange Instructions..........................................................................3-5 Branch Instructions.................................................................................................3-7 Data Processing Instructions ..................................................................................3-9 ARM Shift Operations.............................................................................................3-12 Logical Shift Left ....................................................................................................3-12 Logical Shift Right ..................................................................................................3-13 Arithmetic Shift Right .............................................................................................3-13 Rotate Right ...........................................................................................................3-14 Rotate Right Extended ...........................................................................................3-14 PSR Transfer .........................................................................................................3-19 Multiply Instructions................................................................................................3-22 Multiply Long Instructions .......................................................................................3-25 Single Data Transfer Instructions............................................................................3-28 Little-Endian Offset Addressing ..............................................................................3-30 Halfword and Signed Data Transfer with Register Offset ........................................3-34 Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing .......3-35 Block Data Transfer Instructions.............................................................................3-40 Post-Increment Addressing.....................................................................................3-41 Pre-Increment Addressing ......................................................................................3-42 Post-Decrement Addressing ...................................................................................3-42 Pre-Decrement Addressing.....................................................................................3-43 Swap Instruction.....................................................................................................3-47 Software Interrupt Instruction..................................................................................3-49 Coprocessor Data Operation Instruction .................................................................3-51 Coprocessor Data Transfer Instructions ..................................................................3-53 Coprocessor Register Transfer Instructions ............................................................3-56 Undefined Instruction..............................................................................................3-58 S3C2410X MICROPROCESSOR xix List of Figures (Continued) Figure Number 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 Title Page Number THUMB Instruction Set Formats ............................................................................ 4-2 Format 1................................................................................................................ 4-5 Format 2................................................................................................................ 4-7 Format 3................................................................................................................ 4-9 Format 4................................................................................................................ 4-11 Format 5................................................................................................................ 4-13 Format 6................................................................................................................ 4-16 Format 7................................................................................................................ 4-18 Format 8................................................................................................................ 4-20 Format 9................................................................................................................ 4-22 Format 10.............................................................................................................. 4-24 Format 11.............................................................................................................. 4-26 Format 12.............................................................................................................. 4-28 Format 13.............................................................................................................. 4-30 Format 14.............................................................................................................. 4-31 Format 15.............................................................................................................. 4-33 Format 16.............................................................................................................. 4-34 Format 17.............................................................................................................. 4-36 Format 18.............................................................................................................. 4-37 Format 19.............................................................................................................. 4-38 S3C2410X Memory Map after Reset...................................................................... 5-2 S3C2410X External nWAIT Timing Diagram (Tacc=4) .......................................... 5-5 S3C2410X nXBREQ/nXBACK Timing Diagram ..................................................... 5-6 Memory Interface with 8-bit ROM .......................................................................... 5-7 Memory Interface with 8-bit ROM x 2 .................................................................... 5-7 Memory Interface with 8-bit ROM x 4 .................................................................... 5-8 Memory Interface with 16-bit ROM ........................................................................ 5-8 Memory Interface with 16-bit SRAM ...................................................................... 5-9 Memory Interface with 16-bit SRAM x 2................................................................. 5-9 Memory Interface with 16-bit SDRAM (8MB: 1Mb x 16 x 4banks).......................... 5-10 Memory Interface with 16-bit SDRAM (16MB: 1Mb x 16 x 4banks x 2ea) .............. 5-10 S3C2410X nGCS Timing Diagram......................................................................... 5-11 S3C2410X SDRAM Timing Diagram...................................................................... 5-12 xx S3C2410X MICROPROCESSOR List of Figures (Continued) Figure Number 6-1 6-2 6-3 6-4 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 8-1 8-2 8-3 8-4 8-5 8-6 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 12-1 13-1 Title Page Number NAND Flash Controller Block Diagram ...................................................................6-2 NAND Flash Operation Scheme .............................................................................6-2 TACLS=0, TWRPH0=1, TWRPH1=0 .....................................................................6-3 NAND Flash Memory Mapping ...............................................................................6-5 Clock Generator Block Diagram .............................................................................7-3 PLL (Phase-Locked Loop) Block Diagram ..............................................................7-5 Main Oscillator Circuit Examples............................................................................7-5 Power-On Reset Sequence (when the external clock source is a crystal oscillator).7-6 Changing Slow Clock by Setting PMS Value ..........................................................7-7 Changing CLKDIVN Register Value........................................................................7-8 The Clock Distribution Block Diagram ....................................................................7-9 Power Management State Diagram ........................................................................7-10 Issuing Exit_from_Slow_mode Command in PLL on State .....................................7-12 Issuing Exit_from_Slow_mode Command after Lock Time .....................................7-12 Issuing Exit_from_Slow_mode Command and the Instant PLL_on Command Simultaneously.......................................................................................................7-13 Power-OFF Mode...................................................................................................7-16 Basic DMA Timing Diagram ...................................................................................8-3 Demand/Handshake Mode Comparison..................................................................8-4 Burst 4 Transfer Size..............................................................................................8-5 Single service in Demand Mode with Unit Transfer Size.........................................8-6 Single service in Handshake Mode with Unit Transfer Size.....................................8-6 Whole service in Handshake Mode with Unit Transfer Size ....................................8-6 16-bit PWM Timer Block Diagram ..........................................................................10-2 Timer Operations ...................................................................................................10-3 Example of Double Buffering Function ...................................................................10-4 Example of a Timer Operation ...............................................................................10-6 Example of PWM ...................................................................................................10-7 Inverter On/Off .......................................................................................................10-8 The Wave Form When a Dead Zone Feature is Enabled .......................................10-9 Timer4 DMA Mode Operation.................................................................................10-10 UART Block Diagram (with FIFO)...........................................................................11-2 UART AFC Interface ..............................................................................................11-4 UART Receiving 5 Characters with 2 Errors ...........................................................11-6 IrDA Function Block Diagram .................................................................................11-8 Serial I/O Frame Timing Diagram (Normal UART)..................................................11-9 Infra-Red Transmit Mode Frame Timing Diagram...................................................11-9 Infra-Red Receive Mode Frame Timing Diagram ...................................................11-9 nCTS and Delta CTS Timing Diagram....................................................................11-18 USB Host Controller Block Diagram .......................................................................12-1 USB Device Controller Block Diagram....................................................................13-2 S3C2410X MICROPROCESSOR xxi List of Figures (Continued) Figure Number 14-1 14-2 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 16-1 16-2 16-3 17-1 17-2 18-1 19-1 20-1 20-2 20-3 20-4 20-5 20-8 20-9 21-1 21-2 22-1 24-1 24-2 24-3 24-4 24-5 Title Page Number Interrupt Process Diagram ..................................................................................... 14-1 Priority Generating Block....................................................................................... 14-4 LCD Controller Block Diagram............................................................................... 15-3 Monochrome Display Types (STN) ........................................................................ 15-11 Color Display Types (STN) .................................................................................... 15-12 8-bit Single Scan Display Type STN LCD Timing .................................................. 15-14 16BPP Display Types (TFT) .................................................................................. 15-21 TFT LCD Timing Example..................................................................................... 15-22 Example of Scrolling in Virtual Display (Single Scan) ............................................ 15-24 Example of PWREN Function (PWREN = 1, INVPWREN = 0) .............................. 15-25 ADC and Touch Screen Interface Functional Block Diagram ................................. 16-2 Example of ADC and Touch Screen Interface........................................................ 16-3 Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode..................... 16-6 Real Time Clock Block Diagram ........................................................................... 17-2 Main Oscillator Circuit Example............................................................................. 17-4 Watchdog Timer Block Diagram ............................................................................ 18-2 Block Diagram....................................................................................................... 19-2 IIC-Bus Block Diagram .......................................................................................... 20-2 Start and Stop Condition........................................................................................ 20-3 IIC-Bus Interface Data Format ............................................................................... 20-4 Data Transfer on the IIC-Bus ................................................................................. 20-5 Acknowledge on the IIC-Bus.................................................................................. 20-5 Operations for Slave/Transmitter Mode ................................................................. 20-9 Operations for Slave/Receiver Mode ..................................................................... 20-10 IIS-Bus Block Diagram .......................................................................................... 21-2 IIS-Bus and MSB (Left)-justified Data Interface Formats........................................ 21-4 SPI Block Diagram ................................................................................................ 22-2 Typical Operating Voltage/Frequency Range (VDDIO=3.3V, @Room temperature & SMDK2410 board)............................................................ 24-4 XTIpll Clock Timing ............................................................................................... 24-5 EXTCLK Clock Input Timing .................................................................................. 24-5 EXTCLK/HCLK in case that EXTCLK is used without the PLL................................ 24-5 HCLK/CLKOUT/SCLK in case that EXTCLK is used .............................................. 24-6 xxii S3C2410X MICROPROCESSOR List of Figures (Concluded) Figure Number 24-6 24-7 24-8 24-9 24-10 24-11 24-12 24-13 24-14 24-15 24-16 24-17 24-18 24-19 24-20 24-21 24-22 24-23 24-24 24-25 24-26 24-27 24-28 24-29 24-30 24-31 24-32 24-33 24-34 24-35 24-36 24-37 25-1 25-2 Title Page Number Manual Reset Input Timing.....................................................................................24-6 Power-On Oscillation Setting Timing ......................................................................24-7 Power_OFF Mode Return Oscillation Setting Timing..............................................24-8 ROM/SRAM Burst READ Timing(I) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit) ................24-9 ROM/SRAM Burst READ Timing(II) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit) ................24-10 External Bus Request in ROM/SRAM Cycle (Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0)..................................24-11 ROM/SRAM READ Timing (I) (Tacs=2,Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0)...................................24-12 ROM/SRAM READ Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1)..........................24-13 ROM/SRAM WRITE Timing (I) (Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0 ......................................24-14 ROM/SRAM WRITE Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1)..................................24-15 External nWAIT READ Timing (Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0)..................................24-16 External nWAIT WRITE Timing (Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0)..................................24-16 Masked-ROM Single READ Timing (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11).....24-17 Masked-ROM Consecutive READ Timing (Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11)...............................................24-17 SDRAM Single Burst READ Timing (Trp=2, Trcd=2, Tcl=2, DW=16bit).................24-18 External Bus Request in SDRAM Timing (Trp=2, Trcd=2, Tcl=2)............................24-19 SDRAM MRS Timing..............................................................................................24-20 SDRAM Single READ Timing(I) (Trp=2, Trcd=2, Tcl=2) .........................................24-21 SDRAM Single READ Timing(II) (Trp=2, Trcd=2, Tcl=3) ........................................24-22 SDRAM Auto Refresh Timing (Trp=2, Trc=4) .........................................................24-23 SDRAM Page Hit-Miss READ Timing (Trp=2, Trcd=2, Tcl=2).................................24-24 SDRAM Self Refresh Timing (Trp=2, Trc=4) ..........................................................24-25 SDRAM Single Write Timing (Trp=2, Trcd=2).........................................................24-26 SDRAM Page Hit-Miss Write Timing (Trp=2, Trcd=2, Tcl=2)..................................24-27 External DMA Timing (Handshake, Single transfer)................................................24-28 TFT LCD Controller Timing ....................................................................................24-28 IIS Interface Timing................................................................................................24-29 IIC Interface Timing................................................................................................24-29 SD/MMC Interface Timing ......................................................................................24-30 SPI Interface Timing (CPHA=1, CPOL=1) ..............................................................24-30 NAND Flash Address/Command Timing.................................................................24-31 NAND Flash Data Timig .........................................................................................24-31 272-FBGA-1414 Package Dimension 1 ..................................................................25-1 272-FBGA-1414 Package Dimension 2 ..................................................................25-2 S3C2410X MICROPROCESSOR xxiii List of Tables Table Number 1-1 1-2 1-3 1-4 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 5-1 5-2 7-1 7-2 7-3 Title Page Number 272-Pin FBGA Pin Assignments - Pin Number Order (Sheet 1 of 3) ......................1-7 272-Pin FBGA Pin Assignments (Sheet 1 of 9).......................................................1-10 S3C2410X Signal Descriptions (Sheet 1 of 5).........................................................1-20 S3C2410X Special Registers (Sheet of 1 of 11)......................................................1-25 PSR Mode Bit Values .............................................................................................2-9 Exception Entry/Exit ...............................................................................................2-11 Exception Vectors ..................................................................................................2-13 The ARM Instruction Set ........................................................................................3-2 Condition Code Summary ......................................................................................3-4 ARM Data Processing Instructions..........................................................................3-11 Incremental Cycle Times........................................................................................3-16 Assembler Syntax Descriptions ..............................................................................3-27 Addressing Mode Names........................................................................................3-45 THUMB Instruction Set Opcodes ............................................................................4-3 Summary of Format 1 Instructions..........................................................................4-5 Summary of Format 2 Instructions..........................................................................4-7 Summary of Format 3 Instructions..........................................................................4-9 Summary of Format 4 Instructions..........................................................................4-11 Summary of Format 5 Instructions..........................................................................4-13 Summary of PC-Relative Load Instruction..............................................................4-16 Summary of Format 7 Instructions..........................................................................4-19 Summary of format 8 instructions...........................................................................4-20 Summary of Format 9 Instructions..........................................................................4-23 Halfword Data Transfer Instructions........................................................................4-24 SP-Relative Load/Store Instructions .......................................................................4-26 Load Address .........................................................................................................4-28 The ADD SP Instruction .........................................................................................4-30 PUSH and POP Instructions ...................................................................................4-31 The Multiple Load/Store Instructions.......................................................................4-33 The Conditional Branch Instructions .......................................................................4-34 The SWI Instruction................................................................................................4-36 Summary of Branch Instruction ..............................................................................4-37 The BL Instruction ..................................................................................................4-39 Bank 6/7 Address ...................................................................................................5-2 SDRAM Bank Address configuration ......................................................................5-4 Clock Source Selection at Boot-Up.........................................................................7-2 Clock and Power State in Each Power Mode ..........................................................7-10 CLKSLOW and CLKDIVN Register Settings for SLOW Clock.................................7-11 S3C2410X MICROPROCESSOR xxv List of Tables (Continued) Table Number 8-1 8-2 9-1 11-1 12-1 15-1 15-2 15-3 15-4 15-5 15-6 16-1 16-2 16-3 21-1 21-2 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 24-11 24-12 24-13 24-14 24-15 24-16 24-17 24-18 24-19 24-20 Title Page Number DMA request sources for each channel.................................................................. 8-2 DMA Controller Module Signal Timing Constants .................................................. 8-3 S3C2410X Port Configuration Overview (Sheet 1 of 5).......................................... 9-2 Interrupts in Connection with FIFO ........................................................................ 11-5 OHCI Registers for USB Host Controller................................................................ 12-1 Relation Between VCLK and CLKVAL (STN, HCLK = 60 MHz).............................. 15-5 Dither Duty Cycle Examples .................................................................................. 15-7 Relation Between VCLK and CLKVAL (TFT, HCLK = 60 MHz) .............................. 15-15 5:6:5 Format.......................................................................................................... 15-20 5:5:5:1 Format....................................................................................................... 15-20 MV Value for Each Display Mode .......................................................................... 15-39 Condition of Touch Screen Panel Pads in Separate X/Y Position Conversion Mode .................................................................................................. 16-4 Condition of Touch Screen Panel Pads in Auto (Sequential) X/Y Position Conversion Mode. ................................................................................................. 16-5 Condition of Touch Screen Panel Pads in Waiting for Interrupt Mode. ................... 16-5 CODEC clock (CODECLK = 256 or 384fs)............................................................. 21-4 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs).............................. 21-5 Absolute Maximum Rating..................................................................................... 24-1 Recommended Operating Conditions .................................................................... 24-1 Normal I/O PAD DC Electrical Characteristics ....................................................... 24-2 USB DC Electrical Characteristics ......................................................................... 24-3 S3C2410X Power Supply Voltage and Current ...................................................... 24-3 Typical Current Decrease by CLKCON Register (FCLK@202.8MHz) .................... 24-4 Clock Timing Constants......................................................................................... 24-32 ROM/SRAM Bus Timing Constants ....................................................................... 24-33 Memory Interface Timing Constants (3.3V)............................................................ 24-33 External Bus Request Timing Constants................................................................ 24-34 DMA Controller Module Signal Timing Constants .................................................. 24-34 TFT LCD Controller Module Signal Timing Constants............................................ 24-35 IIS Controller Module Signal Timing Constants...................................................... 24-35 IIC BUS Controller Module Signal Timing .............................................................. 24-36 SD/MMC Interface Transmit/Receive Timing Constants ........................................ 24-36 SPI Interface Transmit/Receive Timing Constants................................................. 24-37 USB Electrical Specifications................................................................................. 24-37 USB Full Speed Output Buffer Electrical Characteristics........................................ 24-38 USB Low Speed Output Buffer Electrical Characteristics ....................................... 24-38 NAND Flash Interface Timing Constants................................................................ 21-39 xxvi S3C2410X MICROPROCESSOR NOTIFICATION OF REVISIONS ORIGINATOR: PRODUCT NAME: DOCUMENT NAME: DOCUMENT NUMBER: EFFECTIVE DATE: SUMMARY: Samsung Electronics, SOC Development Group, Ki-Heung, South Korea S3C2410X RISC Microcontroller S3C2410X User's Manual, Revision 1.2 21.2-S3-C2410X-012003 April 28, 2003 As a result of additional product testing and evaluation, some specifications published in the S3C2410X User's Manual, Revision 1.1, have been changed. These changes for S3C2410X microcontroller are described in detail in the Revision Descriptions section below. DIRECTIONS: Please note the changes in your copy (copies) of the S3C2410X User's Manual, Revision 1.1 Or, simply attach the Revision Descriptions of the next page to S3C2410X User's Manual, Revision 1.1 REVISION HISTORY Revision 1 2 3 Date October , 2002 January , 2003 April 28, 2003 Revision 1.1 Revision 1.2 Remark There is no preliminary specification. This is the first edition. REVISION DESCRIPTIONS ERRATA from S3C2410X User's Manual This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of application, operating systems, or tools. This document may also contain information that was not previously published. [ FORMAT ] 1. PRODUCT OVERVIEW : 1-31 : TABLE 1-4. S3C2410X SPECIAL REGISTERS(SHEET 7 OF 11) : 04/28/2003 Changed Table 1-4 (Sheet 7 of 11). Table 1-4. S3C2410X Special Registers (Sheet 7 of 11) Register Name USB Device MAXP_REG 0x5200018F 0x5200018C Endpoint Max Packet Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function 2. MEMORY CONTROLLER : 5-5 : EXTERNAL nWAIT TIMING DIAGRAM : 04/28/2003 Changed Figure 5-2. HCLK ADDR nGCS Tacs Tacc=4 Tcos Sampling nWAIT Delayed nOE nWAIT DATA(R) Figure 5-2. S3C2410X External nWAIT Timing Diagram (Tacc=4) 3. MEMORY CONTROLLER : 5-17 : REFRESH CONTROL REGISTER : 04/28/2003 Changed descriptions of REFRESH[19:18]. REFRESH Tsrc Bit Description Initial State 11 [19:18] SDRAM Semi Row Cycle Time 00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks SDRAM's Row_Cycle time (Trc) = Tsrc + Trp If) Trp = 3 clocks & Tsrc = 7 clocks, Trc = 3 + 7 = 10 clocks 4. NAND FLASH CONTROLLER : 6-1 : FEATURES : 04/28/2003 Changed a sentence as follows.(fourth line from the bottom) Auto boot mode : The boot code is transferred into Steppingstone after reset. After the transfer, the boot code will be executed on the Steppingstone. 5. CLOCK & POWER MANAGEMENT : 7-19 : PLL VALUE SELECTION GUIDE : 04/28/2003 Changed a sentence as follows. 3. 0.7 < 3.373/sqrt(m) < 1.8 5. 20e6 Fout 300e6 ( The max. Fout of the PLL itself is 300Mhz ) 6. UART : 11-1 : OVERVIEW : 04/28/2003 Changed a sentence as follows.(third line from the top) The UART can support bit rates of up to 230.4K bps using system clock. 7. UART : 11-7 : UART BAUD-RATE GENERATOR ERROR TOLERANCE : 04/28/2003 Added a section at the middle of this page as follows. UART baud-rate generator error tolerance UART 10-bit time error should be less than 1.87%(3/160). tUPCLK = (UBRDIVn + 1) x 16 x 10 / PCLK tUEXACT = 10 / baud-rate tUPCLK : Real UART 10-bit time tUEXACT : Ideal UART 10-bit time UART error = (tUPCLK - tUEXACT) / tUEXACT x 100% 8. UART : 11-16 : UART ERROR STATUS REGISTER : 04/28/2003 Changed a descriptions of UERSTATn[3] and UERSTATn[1]. UERSTATn Reserved Reserved Bit [3] [1] Description 0 = No frame error during receive 1 = Frame error (Interrupt is requested.) 0 = No frame error during receive 1 = Frame error (Interrupt is requested.) Initial State 0 0 9. UART : 11-18 : UART MODEM STATUS REGISTER : 04/28/2003 Changed a sentence as follows There are two UART modem status registers including UMSTAT0 and UMSTAT1 in the UART block. 10. USB DEVICE : 13-19 : MAX PACKET REGISTER (MAXP_REG) : 04/28/2003 Changed a address of MAXP_REG. Register MAXP_REG Address 0x5200018C(L) 0x5200018F(B) R/W R/W (byte) Description End Point MAX packet register Reset Value 0x01 11. LCD CONTROLLER : 15-28 : LCD CONTROL 3 REGISTER : 04/28/2003 Changed a descriptions of LCDCON3[25:19]. LCDCON3 HBPD (TFT) WDLY (STN) Bit [25:19] Description TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. STN: WDLY[1:0] bits determine the delay between VLINE and VCLK by counting the number of the HCLK. WDLY[7:2] are reserved. 00 = 16 HCLK, 01 = 32 HCLK, 10 = 48 HCLK, 11 = 64 HCLK Initial state 0000000 12. LCD CONTROLLER : 15-29 : LCD CONTROL 4 REGISTER : 04/28/2003 Changed a descriptions of LCDCON4[7:0]. LCDCON4 HSPW(TFT) WLH(STN) Bit [7:0] Description TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. STN: WLH[1:0] bits determine the VLINE pulse's high level width by counting the number of the HCLK. WLH[7:2] are reserved. 00 = 16 HCLK, 01 = 32 HCLK, 10 = 48 HCLK, 11 = 64 HCLK Initial state 0X00 13. WATCHDOG TIMER : 18-2 : WATCHDOG TIMER OPERATION : 04/28/2003 Changed a sentence as follows.(fifth line from the top) Valid prescaler values range from 0 to 28-1. 14. WATCHDOG TIMER : 18-3 : WATCHDOG TIMER SPECIAL REGISTERS : 04/28/2003 Changed a descriptions of WTCON[15:8]. WTCON Prescaler Value Bit [15:8] Description Prescaler value. The valid range is from 0 to (28-1). Initial State 0x80 15. ELECTRICAL DATA : 24-3 : POWER SUPPLY VOLTAGE AND CURRENT : 04/28/2003 Changed Table 24-5. Table 24-5. S3C2410X Power Supply Voltage and Current Parameter Typical slow mode power NOTE(3) (Total VDDi + VDDIO) Maximum Power_OFF mode power Typical Power_OFF mode power NOTE(3) Maximum RTC power Typical RTC power NOTE(3) Value 33 Unit mW Condition FCLK = 12MHz (F:H:P = 1:1:1) 80 8 63 3 uA uA uA uA @1.95V/3.6V, Room temperature All other I/O static. @1.95V/3.6V, Room temperature X-tal = 32.768KHz for RTC 16. ELECTRICAL DATA : 24-31 : NAND FLASH TIMING : 04/28/2003 Changed Figure 24-36 and Figure 24-37. TACLS TWRPH0 TWRPH1 TACLS TWRPH0 TWRPH1 HCLK HCLK tCLED CLE tWED nFWE tCLED ALE tALED tALED tWED nFWE tWED tWED tWDS DATA[7:0] COMMAND tWDH DATA[7:0] tWDS ADDRESS tWDH Figure 24-36. NAND Flash Address/Command Timing TWRPH0 TWRPH1 TWRPH0 TWRPH1 HCLK tWED tWED nFWE tWDS DATA[7:0] WDATA HCLK tWED nFRE tWED tWDH DATA[7:0] RDATA tRDS tRDH Figure 24-37. NAND Flash Timing 17. ELECTRICAL DATA : 24-39 : NAND FLASH INTERFACE TIMING CONSTANTS : 04/28/2003 Changed Table 24-20. Table 24-20. NAND Flash Interface Timing Constants (VDDi, VDDalive, VDDiarm = 1.8 V 0.15 V, TA = 0 to 70 C, VDDIO = 3.3V 0.3V) Parameter NFCON Chip Enable delay NFCON CLE delay NFCON ALE delay NFCON Write Enable delay NFCON Read Enable delay NFCON Write Data Setup time NFCON Write Data Hold time NFCON Read Data Setup requirement time NFCON Read Data Hold requirement time Symbol tCED tCLED tALED tWED tRED tWDS tWDH tRDS tRDH Min - - - - - - 1.7 0.3 0.3 Max 6.2 7.1 7.5 7.2 7.1 6.5 - - - Unit ns ns ns ns ns ns ns ns ns S3C2410X PRODUCT OVERVIEW 1 PRODUCT OVERVIEW INTRODUCTION This manual describes SAMSUNG's S3C2410X 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2410X includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation. The S3C2410X was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture called Advanced Microcontroller Bus Architecture (AMBA). The S3C2410X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the S3C2410X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include: * * * * * * * * * * * * * * * 1.8V int., 3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU External memory controller (SDRAM Control and Chip Select logic) LCD controller (up to 4K color STN and 256K color TFT) with 1-ch LCD-dedicated DMA 4-ch DMAs with external request pins 3-ch UART (IrDA1.0, 16-Byte Tx FIFO, and 16-Byte Rx FIFO) / 2-ch SPI 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller SD Host interface version 1.0 & Multi-Media Card Protocol version 2.11 compatible 2-port USB Host /1- port USB Device (ver 1.1) 4-ch PWM timers & 1-ch internal timer Watch Dog Timer 117-bit general purpose I/O ports / 24-ch external interrupt source Power control: Normal, Slow, Idle and Power-off mode 8-ch 10-bit ADC and Touch screen interface RTC with calendar function On-chip clock generator with PLL 1-1 PRODUCT OVERVIEW S3C2410X FEATURES Architecture * * * * NAND Flash Boot Loader * * * Integrated system for hand-held devices and general embedded applications 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance ARM920T CPU core supports the ARM debug architecture. Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB) Supports booting from NAND flash memory 4KB internal buffer for booting Supports storage memory for NAND flash memory after booting Cache Memory * * * * * 64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB) 8words length per line with one valid bit and two dirty bits per line Pseudo random or round robin replacement algorithm Write-through or write-back cache operation to update the main memory The write buffer can hold 16 words of data and four addresses. * * System Manager * * * * * * Little/Big Endian support Address space: 128M bytes for each bank (total 1G bytes) Supports programmable 8/16/32-bit data bus width for each bank Fixed bank start address from bank 0 to bank 6 Programmable bank start address and bank size for bank 7 Eight memory banks: * * Clock & Power Manager * On-chip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum 203Mhz @ 1.8V. Clock can be fed selectively to each function block by software. Power mode: Normal, Slow, Idle, and Power-off mode Normal mode: Normal operating mode Slow mode: Low frequency clock without PLL Idle mode: The clock for only CPU is stopped. Power-off mode: The Core power including all peripherals is shut down. Woken up by EINT[15:0] or RTC alarm interrupt from Power-Off mode - Six memory banks for ROM, SRAM, and others. - Two memory banks for ROM/SRAM/ Synchronous DRAM * * * * Fully Programmable access cycles for all memory banks Supports external wait signals to expend the bus cycle Supports self-refresh mode in SDRAM for powerdown Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others) * 1-2 S3C2410X PRODUCT OVERVIEW FEATURES (Continued) Interrupt Controller * 16-byte Rx FIFO. DMA Controller * * * 55 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, and 1 Battery Fault) Level/Edge mode on external interrupt source Programmable polarity of edge and level Supports Fast Interrupt request (FIQ) for very urgent interrupt request 4-ch DMA controller Supports memory to memory, IO to memory, memory to IO, and IO to IO transfers Burst transfer mode to enhance the transfer rate * * * A/D Converter & Touch Screen Interface * * Timer with Pulse Width Modulation (PWM) * 8-ch multiplexed ADC Max. 500KSPS and 10-bit Resolution 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation Programmable duty cycle, frequency, and polarity Dead-zone generation Supports external clock sources LCD Controller STN LCD Displays Feature * * * * Supports 3 types of STN LCD panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display type Supports monochrome mode, 4 gray levels, 16 gray levels, 256 colors and 4096 colors for STN LCD Supports multiple screen size - Typical actual screen size: 640x480, 320x240, 160x160, and others - Maximum virtual screen size is 4 Mbytes. - Maximum virtual screen size in 256 color mode: 4096x1024, 2048x2048, 1024x4096, and others * RTC (Real Time Clock) * * * * * Full clock feature: second, minute, hour, date, day, month, and year 32.768 KHz operation Alarm interrupt Time tick interrupt General Purpose Input/Output Ports * * 24 external interrupt ports multiplexed input/output ports TFT(Thin Film Transistor) Color Displays Feature * * * * Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color TFT Supports 16 bpp non-palette true-color displays for color TFT Supports maximum 16M color TFT at 24 bpp mode Supports multiple screen size - Typical actual screen size: 640x480, 320x240, 160x160, and others - Maximum virtual screen size is 4Mbytes. - Maximum virtual screen size in 64K color mode: 2048x1024, and others UART * * * * * * * 3-channel UART with DMA-based or interruptbased operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive (Tx/Rx) Supports external clocks for the UART operation (UCLK) Programmable baud rate Supports IrDA 1.0 Loopback mode for testing Each channel has internal 16-byte Tx FIFO and 1-3 PRODUCT OVERVIEW S3C2410X FEATURES (Continued) Watchdog Timer * * SD Host Interface * * 16-bit Watchdog Timer Interrupt request or system reset at time-out Compatible with SD Memory Card Protocol version 1.0 Compatible with SDIO Card Protocol version 1.0 Bytes FIFO for Tx/Rx DMA based or Interrupt based operation Compatible with Multimedia Card Protocol version 2.11 IIC-Bus Interface * * * * * 1-ch Multi-Master IIC-Bus Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode. SPI Interface IIS-Bus Interface * * * * * * * 1-ch IIS-bus for audio interface with DMA-based operation Serial, 8-/16-bit per channel data transfers 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx Supports IIS format and MSB-justified data format Compatible with 2-ch Serial Peripheral Interface Protocol version 2.11 2x8 bits Shift register for Tx/Rx DMA-based or interrupt-based operation Operating Voltage Range * * * Core: 1.8V Memory : 3.3V SDRAM or VDD = 1.8/2.5V & VDDQ = 3.0/3.3V Mobile SDRAM I/O : 3.3V USB Host * * * 2-port USB Host Complies with OHCI Rev. 1.0 Compatible with USB Specification version 1.1 Operating Frequency * Up to 203MHz USB Device * * * 1-port USB Device 5 Endpoints for USB Device Compatible with USB Specification version 1.1 Package * 272-FBGA 1-4 S3C2410X PRODUCT OVERVIEW BLOCK DIAGRAM ARM920T Instruction MMU C13 IV2A[31:0] ARM9TDMI Processor core (Internal Embedded ICE) DD[31:0] DV2A[31:0] C13 Data MMU DPA[31:0] Data CACHE (16KB) WriteBack PA Tag RAM WBPA[31:0] DVA[31:0] ID[31:0] CP15 Write Buffer AMBA Bus I/F IPA[31:0] Instruction CACHE (16KB) External Coproc Interface JTAG LCD CONT. LCD DMA USB Host CONT. A H B B U S Bridge & DMA (4Ch) BUS CONT. Arbitor/Decode Interrupt CONT. Power Management Memory CONT. SRAM/NOR/SDRAM ExtMaster NAND CONT. NAND Flash Boot Loader Clock Generator (MPLL) UART 0, 1, 2 USB Device SDI/MMC Watchdog Timer BUS CONT. Arbitor/Decode SPI 0, 1 SPI I2C A P B B U S I2S GPIO RTC ADC Timer/PWM 0 ~ 3, 4(Internal) Figure 1-1. S3C2410X Block Diagram 1-5 PRODUCT OVERVIEW S3C2410X PIN ASSIGNMENTS U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 BOTTOM VIEW Figure 1-2. S3C2410X Pin Assignments (272-FBGA) 1-6 S3C2410X PRODUCT OVERVIEW Table 1-1. 272-Pin FBGA Pin Assignments - Pin Number Order (Sheet 1 of 3) Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 Pin Name DATA19 DATA18 DATA16 DATA15 DATA11 VDDMOP DATA6 DATA1 ADDR21/GPA6 ADDR16/GPA1 ADDR13 VSSMOP ADDR6 ADDR2 VDDMOP nBE3:nWBE3:DQM3 nBE0:nWBE0:DQM0 DATA22 DATA20 DATA17 VDDMOP DATA13 DATA9 DATA5 DATA0 ADDR24/GPA9 ADDR17/GPA2 ADDR12 ADDR8 ADDR4 Pin Number B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 nSRAS nBE1:nWBE1:DQM1 VSSi DATA24 DATA23 DATA21 VDDi DATA12 DATA7 DATA4 VDDi ADDR25/GPA10 VSSMOP ADDR14 ADDR7 ADDR3 nSCAS nBE2:nWBE2:DQM2 nOE VDDi DATA27 DATA25 VSSMOP DATA26 DATA14 DATA10 DATA2 VDDMOP ADDR22/GPA7 Pin Name ADDR0/GPA0 Pin Number D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 VDDi ADDR10 ADDR5 ADDR1 VSSMOP SCKE nGCS0 DATA31 DATA29 DATA28 DATA30 VDDMOP VSSMOP DATA3 ADDR26/GPA11 ADDR23/GPA8 ADDR18/GPA3 VDDMOP ADDR11 nWE nGCS3/GPA14 nGCS1/GPA12 nGCS2/GPA13 nGCS4/GPA15 TOUT1/GPB1 TOUT0/GPB0 VSSMOP TOUT2/GPB2 VSSOP Pin Name ADDR19/GPA4 1-7 PRODUCT OVERVIEW S3C2410X Table 1-1. 272-Pin FBGA Pin Assignments - Pin Number Order (Sheet 2 of 3) Pin Number F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 G1 G2 G3 G4 G5 G6 G7 G9 G11 G12 G13 G14 G15 G16 G17 H1 H2 H3 VSSi DATA8 VSSMOP VSSi ADDR20/GPA5 VSSi VSSMOP SCLK0 SCLK1 nGCS5/GPA16 nGCS6:nSCS0 nGCS7:nSCS1 nXBACK/GPB5 nXDACK1/GPB7 TOUT3/GPB3 TCLK0/GPB4 nXBREQ/GPB6 VDDalive VDDiarm VSSMOP ADDR15 ADDR9 nWAIT ALE/GPA18 nFWE/GPA19 nFRE/GPA20 nFCE/GPA22 VSSiarm nXDACK0/GPB9 nXDREQ0/GPB10 Pin Name Pin Number H4 H5 H6 H12 H13 H14 H15 H16 H17 J1 J2 J3 J4 J5 J6 J7 J11 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K12 nTRST TCK CLE/GPA17 VSSOP VDDMOP VSSi XTOpll XTIpll TDI VCLK:LCD_HCLK/GPC1 TMS LEND:STH/GPC0 TDO VLINE:HSYNC:CPV/GPC2 Pin Name nXDREQ1/GPB8 Pin Number K13 K14 K15 K16 K17 L1 L2 L3 L4 L5 L6 L7 L9 L11 L12 L13 L14 L15 L16 L17 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 Pin Name TXD2/nRTS1/GPH6 RXD1/GPH5 TXD0/GPH2 TXD1/GPH4 RXD0/GPH3 VD0/GPC8 VD1/GPC9 LCDVF2/GPC7 VD2/GPC10 VDDiarm LCDVF1/GPC6 IICSCL/GPE14 EINT11/nSS1/GPG3 VDDi_UPLL nRTS0/GPH1 UPLLCAP nCTS0/GPH0 EINT6/GPF6 UCLK/GPH8 EINT7/GPF7 VSSiarm VD5/GPC13 VD3/GPC11 VD4/GPC12 VSSiarm VDDOP VDDiarm IICSDA/GPE15 VSSiarm DP1/PDP0 VSSiarm EXTCLK nRESET VDDi VDDalive PWREN nRSTOUT/GPA21 nBATT_FLT VDDOP VM:VDEN:TP/GPC4 VDDiarm VFRAME:VSYNC:STV/GPC3 VSSOP LCDVF0/GPC5 RXD2/nCTS1/GPH7 1-8 S3C2410X PRODUCT OVERVIEW Table 1-1. 272-Pin FBGA Pin Assignments - Pin Number Order (Sheet 3 of 3) Pin Number M11 M12 M13 M14 M15 M16 M17 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 Pin Name EINT23/nYPON/GPG15 RTCVDD VSSi_MPLL EINT5/GPF5 EINT4/GPF4 EINT2/GPF2 EINT3/GPF3 VD6/GPC14 VD8/GPD0 VD7/GPC15 VD9/GPD1 VDDiarm CDCLK/GPE2 SDDAT1/GPE8 VSSiarm VDDOP VDDiarm DN1/PDN0 Vref AIN7 EINT0/GPF0 VSSi_UPLL VDDOP EINT1/GPF1 VD10/GPD2 VD12/GPD4 VD11/GPD3 VD23/nSS0/GPD15 I2SSCLK/GPE1 SDCMD/GPE6 SDDAT2/GPE9 Pin Number P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 Pin Name SPICLK0/GPE13 EINT12/LCD_PWREN/GPG4 Pin Number T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 - Pin Name I2SLRCK/GPE0 SDCLK/GPE5 SPIMISO0/GPE11 EINT10/nSS0/GPG2 VSSOP EINT17/GPG9 EINT22/YMON/GPG14 DN0 OM3 VSSA_ADC AIN1 AIN3 AIN5 VD15/GPD7 VD19/GPD11 VD21/GPD13 VSSiarm I2SSDI/nSS0/GPE3 I2SSDO/I2SSDI/GPE4 SPIMOSI0/GPE12 EINT9/GPG1 EINT13/SPIMISO1/GPG5 EINT18/GPG10 EINT20/XMON/GPG12 VSSOP DP0 VDDi_MPLL VDDA_ADC XTIrtc MPLLCAP VDDiarm VD14/GPD6 VD17/GPD9 VD18/GPD10 VSSOP SDDAT0/GPE7 SDDAT3/GPE10 EINT8/GPG0 EINT14/SPIMOSI1/GPG6 EINT15/SPICLK1/GPG7 EINT19/TCLK1/GPG11 CLKOUT0/GPH9 R/nB OM0 AIN4 AIN6 XTOrtc VD13/GPD5 VD16/GPD8 VD20/GPD12 VD22/nSS1/GPD14 EINT16/GPG8 EINT21/nXPON/GPG13 CLKOUT1/GPH10 NCON OM2 OM1 AIN0 AIN2 - 1-9 PRODUCT OVERVIEW S3C2410X Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 1 of 9) Pin Number Pin Name DATA21 DATA22 DATA23 VSSMOP VDDMOP DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 VSSMOP VSSOP TOUT0/GPB0 TOUT1/GPB1 TOUT2/GPB2 TOUT3/GPB3 TCLK0/GPB4 nXBACK/GPB5 nXBREQ/GPB6 nXDACK1/GPB7 VDDalive VDDiarm VSSiarm nXDREQ1/GPB8 nXDACK0/GPB9 nXDREQ0/GPB10 nTRST TCK TDI TMS Default Function DATA21 DATA22 DATA23 VSSMOP VDDMOP DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 VSSMOP VSSOP GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDDalive VDDiarm VSSiarm GPB8 GPB9 GPB10 nTRST TCK TDI TMS I/O State @BUS REQ Hi-z Hi-z Hi-z P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P P -/- -/- -/- -/- -/- -/- -/- -/- P P P -/- -/- -/- I I I I I/O State @PWR-off Hi-z Hi-z Hi-z P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P P O(L)/- O(L)/- O(L)/- O(L)/- -/- -/- -/- -/- P P P -/- -/- -/- I I I I I/O State @nRESET I I I P P I I I I I I I I P P I I I I I I I I P P P I I I I I I I I/O Type t12 t12 t12 s3o d3o t12 t12 t12 t12 t12 t12 t12 t12 s3o s3o t8 t8 t8 t8 t8 t8 t8 t8 d1i d1c s3i t8 t8 t8 is is is is C3 B1 C2 D3 E5 C1 D2 D4 D1 E3 E2 E4 E1 F3 F5 F2 F1 F4 G3 G4 G1 G5 G2 G6 G7 H1 H4 H2 H3 H5 H6 J1 J3 1-10 S3C2410X PRODUCT OVERVIEW Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 2 of 9) Pin Number Pin Name TDO LEND:STH/GPC0 VCLK:LCD_HCLK/GPC1 VLINE:HSYNC:CPV/GPC2 VDDiarm VSSiarm VM:VDEN:TP/GPC4 VFRAME:VSYNC:STV/GPC3 Default Function TDO GPC0 GPC1 GPC2 VDDiarm VSSiarm GPC4 GPC3 VDDOP VSSOP GPC5 GPC6 GPC7 GPC8 GPC9 GPC10 GPC11 VDDiarm VSSiarm GPC12 GPC13 GPC14 GPC15 GPD0 GPD1 GPD2 GPD3 GPD4 VDDiarm VSSiarm GPD5 GPD6 GPD7 I/O State @BUS REQ O -/- -/- -/- P P -/- -/- P P -/- -/- -/- -/- -/- -/- -/- P P -/- -/- -/- -/- -/- -/- -/- -/- -/- P P -/- -/- -/- I/O State @PWR-off O O(L)/- O(L)/- O(L)/- P P O(L)/- O(L)/- P P O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- P P O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- P P O(L)/- O(L)/- O(L)/- I/O State @nRESET O I I I P P I I P P I I I I I I I P P I I I I I I I I I P P I I I I/O Type ot t8 t8 t8 d1c s3i t8 t8 d3o s3o t8 t8 t8 t8 t8 t8 t8 d1c s3i t8 t8 t8 t8 t8 t8 t8 t8 t8 d1c s3i t8 t8 t8 J5 J4 J2 J6 K3 J7 K2 K4 K1 K5 K6 L6 L3 L1 L2 L4 M3 L5 M1 M4 M2 N1 N3 N2 N4 P1 P3 P2 R1 M5 T1 R2 U1 VDDOP VSSOP LCDVF0/GPC5 LCDVF1/GPC6 LCDVF2/GPC7 VD0/GPC8 VD1/GPC9 VD2/GPC10 VD3/GPC11 VDDiarm VSSiarm VD4/GPC12 VD5/GPC13 VD6/GPC14 VD7/GPC15 VD8/GPD0 VD9/GPD1 VD10/GPD2 VD11/GPD3 VD12/GPD4 VDDiarm VSSiarm VD13/GPD5 VD14/GPD6 VD15/GPD7 1-11 PRODUCT OVERVIEW S3C2410X Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 3 of 9) Pin Number Pin Name VD16/GPD8 VD17/GPD9 VD18/GPD10 VD19/GPD11 VD20/GPD12 VD21/GPD13 VD22/nSS1/GPD14 VD23/nSS0/GPD15 VDDiarm VSSiarm VDDOP VSSOP I2SLRCK/GPE0 I2SSCLK/GPE1 CDCLK/GPE2 I2SSDI/nSS0/GPE3 I2SSDO/I2SSDI/GPE4 SDCLK/GPE5 SDCMD/GPE6 SDDAT0/GPE7 SDDAT1/GPE8 SDDAT2/GPE9 SDDAT3/GPE10 SPIMISO0/GPE11 SPIMOSI0/GPE12 SPICLK0/GPE13 VDDiarm VSSiarm IICSCL/GPE14 IICSDA/GPE15 EINT8/GPG0 EINT9/GPG1 EINT10/nSS0/GPG2 Default Function GPD8 GPD9 GPD10 GPD11 GPD12 GPD13 GPD14 GPD15 VDDiarm VSSiarm VDDOP VSSOP GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 GPE8 GPE9 GPE10 GPE11 GPE12 GPE13 VDDiarm VSSiarm GPE14 GPE15 GPG0 GPG1 GPG2 I/O State @BUS REQ -/- -/- -/- -/- -/- -/- -/- -/- P P P P -/- -/- -/- -/-/- -/-/- -/- -/- -/- -/- -/- -/- -/- -/- -/- P P -/- -/- -/- -/- -/-/- I/O State @PWR-off O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- O(L)/- P P P P O(L)/- O(L)/- O(L)/- -/-/- O(L)/-/- O(L)/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- P P Hi-z/- Hi-z/- -/- -/- -/-/- I/O State @nRESET I I I I I I I I P P P P I I I I I I I I I I I I I I P P I I I I I I/O Type t8 t8 t8 t8 t8 t8 t8 t8 d1c s3i d3o s3o t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 d1c s3i d8 d8 t8 t8 t8 T2 R3 R4 U2 T3 U3 T4 P4 N5 U4 M6 R5 T5 P5 N6 U5 U6 T6 P6 R6 N7 P7 R7 T7 U7 P8 M7 N8 L7 M8 R8 U8 T8 1-12 S3C2410X PRODUCT OVERVIEW Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 4 of 9) Pin Number Pin Name EINT11/nSS1/GPG3 EINT12/LCD_PWREN/GPG4 Default Function GPG3 GPG4 GPG5 GPG6 VSSOP VDDOP VDDiarm VSSiarm GPG7 GPG8 GPG9 GPG10 GPG11 GPG12 GPG13 GPG14 GPG15 GPH9 GPH10 DP1 DN1 DP0 DN0 NCON R/nB OM3 OM2 OM1 OM0 VSSOP VSSA_ADC I/O State @BUS REQ -/-/- -/-/- -/-/- -/-/- P P P P -/-/- -/- -/- -/- -/-/- -/-/- -/-/- -/-/- -/-/- -/- -/- - - - - - - - - - - P P - - I/O State @PWR-off -/-/- -/O(L)/- -/Hi-z/- -/Hi-z/- P P P P -/Hi-z/- -/- -/- -/- -/-/- -/O(L)/- -/O(L)/- -/O(L)/- -/O(L)/- O(L)/- O(L)/- - - - - - - - - - - P P - - I/O State @nRESET I I I I P P P P I I I I I I I I I I I AI AI AI AI I I I I I I P P AI AI I/O Type t8 t8 t8 t8 s3o d3o d1c s3i t8 t6 t6 t6 t12 t12 t12 t12 t12 t12 t12 us us us us is is is is is is s3o s3t ia r10 L9 P9 U9 R9 T9 N9 N10 M9 R10 U10 T10 P10 R11 P11 U11 T11 M11 R12 U12 M10 N11 P13 T12 U13 R13 T13 U14 U15 R14 P12 T14 N12 U16 EINT13/SPIMISO1/GPG5 EINT14/SPIMOSI1/GPG6 VSSOP VDDOP VDDiarm VSSiarm EINT15/SPICLK1/GPG7 EINT16/GPG8 EINT17/GPG9 EINT18/GPG10 EINT19/TCLK1/GPG11 EINT20/XMON/GPG12 EINT21/nXPON/GPG13 EINT22/YMON/GPG14 EINT23/nYPON/GPG15 CLKOUT0/GPH9 CLKOUT1/GPH10 DP1/PDP0 DN1/PDN0 DP0 DN0 NCON R/nB OM3 OM2 OM1 OM0 VSSOP VSSA_ADC Vref AIN0 Vref AIN0 1-13 PRODUCT OVERVIEW S3C2410X Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 5 of 9) Pin Number Pin Name AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDDA_ADC XTOrtc XTIrtc RTCVDD VDDi_MPLL VSSi_MPLL MPLLCAP VDDi_UPLL VSSi_UPLL UPLLCAP VDDOP EINT0/GPF0 EINT1/GPF1 EINT2/GPF2 EINT3/GPF3 EINT4/GPF4 EINT5/GPF5 EINT6/GPF6 EINT7/GPF7 UCLK/GPH8 nCTS0/GPH0 nRTS0/GPH1 TXD0/GPH2 RXD0/GPH3 TXD1/GPH4 RXD1/GPH5 Default Function AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDDA_ADC I/O State @BUS REQ - - - - - - - P - - P P P - P P - P -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- I/O State @PWR-off - - - - - - - P - - P P P - P P - P -/- -/- -/- -/- -/- -/- -/- -/- -/- -/- O(H)/- O(H)/- -/- O(H)/- -/- I/O State @nRESET AI AI AI AI AI AI AI P AO AI P P P AI P P AI P I I I I I I I I I I I I I I I I/O Type r10 r10 r10 r10 r10 r10 r10 d3t gp gp d1i d1c s3i gp d1c s3i gp d3o t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 t8 T15 U17 T16 R15 T17 R16 N13 P15 R17 P16 M12 P14 M13 P17 L11 N15 L13 N16 N14 N17 M16 M17 M15 M14 L15 L17 L16 L14 L12 K15 K17 K16 K14 XTOrtc XTIrtc RTCVDD VDDi_MPLL VSSi_MPLL MPLLCAP VDDi_UPLL VSSi_UPLL UPLLCAP VDDOP GPF0 GPF1 GPF2 GPF3 GPF4 GPF5 GPF6 GPF7 GPH8 GPH0 GPH1 GPH2 GPH3 GPH4 GPH5 1-14 S3C2410X PRODUCT OVERVIEW Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 6 of 9) Pin Number Pin Name TXD2/nRTS1/GPH6 RXD2/nCTS1/GPH7 nBATT_FLT nRSTOUT/GPA21 PWREN nRESET VDDalive EXTCLK VDDi XTIpll XTOpll VSSi VSSOP VDDMOP nFCE/GPA22 nFRE/GPA20 nFWE/GPA19 ALE/GPA18 CLE/GPA17 nWAIT nGCS7:nSCS1 nGCS6:nSCS0 nGCS5/GPA16 nGCS4/GPA15 nGCS3/GPA14 nGCS2/GPA13 nGCS1/GPA12 nGCS0 SCKE VSSMOP SCLK1 VDDi SCLK0 Default Function GPH6 GPH7 nBATT_FLT I/O State @BUS REQ -/- -/- - -/- O(H) - P - P - - P P P O(H)/- O(H)/- O(H)/- O(L)/- O(L)/- - Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P Hi-z P Hi-z I/O State @PWR-off O(H)/- -/- - O(L)/- O(L) - P - P - - P P P O(H)/- O(H)/- O(H)/- O(L)/- O(L)/- - O(H) O(H) O(H)/- O(H)/- O(H)/- O(H)/- O(H)/- O(H) O(L) P O(L) P O(L) I/O State @nRESET I I I O(L) O(H) I P AI P AI AO P P P O(H) O(H) O(H) O(L) O(L) I O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) P O(SCLK) P O(SCLK) I/O Type t8 t8 is b8 b8 is d1i is d1c m26 m26 s3i s3o d3o b8 b8 b8 b8 b8 is ot ot ot ot ot ot ot ot ot s3o t16 d1c t16 K13 K12 J17 J16 J15 J12 J14 J11 J13 H17 H16 H15 H13 H14 G17 G16 G15 G14 H12 G13 F17 F16 F15 E17 E14 E16 E15 D17 D16 D15 F14 C17 F13 nRSTOUT PWREN nRESET VDDalive EXTCLK VDDi XTIpll XTOpll VSSi VSSOP VDDMOP nFCE nFRE nFWE ALE CLE nWAIT nGCS7 nGCS6 nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 nGCS0 SCKE VSSMOP SCLK1 VDDi SCLK0 1-15 PRODUCT OVERVIEW S3C2410X Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 7 of 9) Pin Number Pin Name VSSi nWE nOE nBE0:nWBE0:DQM0 nBE1:nWBE1:DQM1 nBE2:nWBE2:DQM2 nBE3:nWBE3:DQM3 nSRAS nSCAS VDDMOP VSSMOP ADDR0/GPA0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 VSSMOP VDDMOP ADDR10 ADDR11 VDDi VSSi ADDR12 ADDR13 ADDR14 ADDR15 ADDR16/GPA1 ADDR17/GPA2 Default Function VSSi nWE nOE DQM0 DQM1 DQM2 DQM3 nSRAS nSCAS VDDMOP VSSMOP ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 VSSMOP VDDMOP ADDR10 ADDR11 VDDi VSSi ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 I/O State @BUS REQ P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P P Hi-z/- Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P P Hi-z Hi-z P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z I/O State @PWR-off P O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) P P O(L)/- O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) P P O(L) O(L) P P O(L) O(L) O(L) O(L) O(L)/- O(L)/- I/O State @nRESET P O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) P P O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) P P O(L) O(L) P P O(L) O(L) O(L) O(L) O(L) O(L) I/O Type s3i ot ot ot ot ot ot ot ot d3o s3o ot ot ot ot ot ot ot ot ot ot s3o d3o ot ot d1c s3i ot ot ot ot ot ot B17 E13 C16 A17 B16 C15 A16 B15 C14 A15 F12 B14 D14 A14 C13 B13 D13 A13 C12 B12 G12 A12 E11 D12 E12 D11 F11 B11 A11 C11 G11 A10 B10 1-16 S3C2410X PRODUCT OVERVIEW Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 8 of 9) Pin Number Pin Name VSSMOP ADDR18/GPA3 ADDR19/GPA4 ADDR20/GPA5 ADDR21/GPA6 ADDR22/GPA7 ADDR23/GPA8 ADDR24/GPA9 ADDR25/GPA10 ADDR26/GPA11 VDDi VSSi VDDMOP VSSMOP DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDMOP VSSMOP DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VDDMOP Default Function VSSMOP ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 ADDR26 VDDi VSSi VDDMOP VSSMOP DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDMOP VSSMOP DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VDDMOP I/O State @BUS REQ P Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- P P P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P I/O State @PWR-off P O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) P P P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P I/O State @nRESET P O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) P P P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P P Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P I/O Type s3o ot ot ot ot ot ot ot ot ot d1c s3i d3o s3o t12 t12 t12 t12 t12 t12 t12 t12 d3o s3o t12 t12 t12 t12 t12 t12 t12 t12 d3o C10 E10 D10 F10 A9 D9 E9 B9 C9 E8 C8 F9 D8 G9 B8 A8 D7 E7 C7 B7 A7 C6 A6 F8 F7 B6 D6 A5 C5 B5 D5 A4 B4 1-17 PRODUCT OVERVIEW S3C2410X Table 1-2. 272-Pin FBGA Pin Assignments (Sheet 9 of 9) Pin Number Pin Name VSSMOP VDDi VSSi DATA16 DATA17 DATA18 DATA19 DATA20 Default Function VSSMOP VDDi VSSi DATA16 DATA17 DATA18 DATA19 DATA20 I/O State @BUS REQ P P P Hi-z Hi-z Hi-z Hi-z Hi-z I/O State @PWR-off P P P Hi-z Hi-z Hi-z Hi-z Hi-z I/O State @nRESET P P P Hi-z Hi-z Hi-z Hi-z Hi-z I/O Type s3o d1c s3i t12 t12 t12 t12 t12 E6 C4 F6 A3 B3 A2 A1 B2 NOTES: 1. The @BUS REQ. shows the pin states at the external bus, which is used by the other bus master. 2. ' - ` mark indicates the unchanged pin state at Bus Request mode. 3. Hi-z or Pre means Hi-z or Previous state and it is determined by the setting of MISCCR register. 4. AI/AO means analog input/analog output. 5. P, I, and O mean power, input and output respectively. 6. The I/O state @nRESET shows the pin status in the @nRESET duration below. 4FCLK nRESET @nRESET FCLK 1-18 S3C2410X PRODUCT OVERVIEW 7. The table below shows I/O types and the descriptions. I/O Type d1i(vdd1ih), s3i(vss3i) d1c(vdd1ih_core), s3i(vss3i) d3o(vdd3op), s3o(vss3op) is(phis) us(pbusb) ot(phot8) b8(phob8) t16(phot16sm) r10(phiar10_abb) ia(phia_abb) gp(phgpad_option) m26(phsoscm26) t6(phtbsu100ct6sm) t8(phbsu100ct8sm) t12(phbsu100ct12sm) d8(phbsu100cd8sm) 1.8V Vdd/Vss for internal logic Descriptions 1.8V Vdd/Vss for internal logic without input driver 3.3V Vdd/Vss for external logic Input pad, LVCMOS schmitt-trigger level USB pad Output pad, tri-state, Io=8mA Output pad, Io=8mA Output pad, tri-state, medium slew rate, Io=16mA Analog input pad with 10-ohm resistor Analog input pad Pad for analog pin Oscillator cell with enable and feedback resistor Bi-directional pad, 5V tolerant LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=6mA Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=8mA Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, tri-state, Io=12mA Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with control, open-drain, Io=8mA d3t(vdd3t_abb), s3t(vss3t_abb) 3.3V Vdd/Vss for analog circuitry 1-19 PRODUCT OVERVIEW S3C2410X SIGNAL DESCRIPTIONS Table 1-3. S3C2410X Signal Descriptions (Sheet 1 of 5) Signal Bus Controller OM[1:0] I OM[1:0] sets S3C2410X in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0. The pull-up/down resistor determines the logic level during the RESET cycle. 00:Nand-boot ADDR[26:0] DATA[31:0] nGCS[7:0] O IO O 01:16-bit 10:32-bit 11:Test mode ADDR[26:0] (Address Bus) outputs the memory address of the corresponding bank . DATA[31:0] (Data Bus) inputs data during memory read and outputs data during memory write. The bus width is programmable among 8/16/32-bit. nGCS[7:0] (General Chip Select) are activated when the address of a memory is within the address region of each bank. The number of access cycles and the bank size can be programmed. nWE (Write Enable) indicates that the current bus cycle is a write cycle. nOE (Output Enable) indicates that the current bus cycle is a read cycle. nXBREQ (Bus Hold Request) allows another bus master to request control of the local bus. BACK active indicates that bus control has been granted. nXBACK (Bus Hold Acknowledge) indicates that the S3C2410X has surrendered control of the local bus to another bus master. nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus cycle cannot be completed. SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Chip Select SDRAM Data Mask SDRAM Clock SDRAM Clock Enable Upper Byte/Lower Byte Enable(In case of 16-bit SRAM) Write Byte Enable Command Latch Enable Address Latch Enable Nand Flash Chip Enable Nand Flash Read Enable Nand Flash Write Enable Nand Flash Configuration Nand Flash Ready/Busy I/O Descriptions nWE nOE nXBREQ nXBACK nWAIT SDRAM/SRAM nSRAS nSCAS nSCS[1:0] DQM[3:0] SCLK[1:0] SCKE nBE[3:0] nWBE[3:0] NAND Flash CLE ALE nFCE nFRE nFWE NCON R/nB O O I O I O O O O O O O O O O O O O I I 1-20 S3C2410X PRODUCT OVERVIEW Table 1-3. S3C2410X Signal Descriptions (Sheet 2 of 5) Signal LCD Control Unit VD[23:0] LCD_PWREN VCLK VFRAME VLINE VM VSYNC HSYNC VDEN LEND STV CPV LCD_HCLK TP STH LCDVF[2:0] EINT[23:0] DMA nXDREQ[1:0] nXDACK[1:0] UART RxD[2:0] TxD[2:0] nCTS[1:0] nRTS[1:0] UCLK ADC AIN[7:0] Vref IIC-Bus IICSDA IICSCL IO IO IIC-bus data IIC-bus clock AI AI ADC input[7:0]. If it isn't used pin, it has to be Low (Ground). ADC Vref I O I O I UART receives data input UART transmits data output UART clear to send input signal UART request to send output signal UART clock signal I O External DMA request External DMA acknowledge O O O O O O O O O O O O O O O O I STN/TFT/SEC TFT: LCD Data Bus STN/TFT/SEC TFT: LCD panel power enable control signal STN/TFT: LCD clock signal STN: LCD Frame signal STN: LCD line signal STN: VM alternates the polarity of the row and column voltage TFT: Vertical synchronous signal TFT: Horizontal synchronous signal TFT: Data enable signal TFT: Line End signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal SEC TFT: Timing control signal for specific TFT LCD(OE/REV/REVB) External Interrupt request I/O Descriptions Interrupt Control Unit 1-21 PRODUCT OVERVIEW S3C2410X Table 1-3. S3C2410X Signal Descriptions (Sheet 3 of 5) Signal IIS-Bus I2SLRCK I2SSDO I2SSDI I2SSCLK CDCLK Touch Screen nXPON XMON nYPON YMON USB Host DN[1:0] DP[1:0] USB Device PDN0 PDP0 SPI SPIMISO[1:0] SPIMOSI[1:0] SPICLK[1:0] nSS[1:0] SD SDDAT[3:0] SDCMD SDCLK General Port GPn[116:0] TIMMER/PWM TOUT[3:0] TCLK[1:0] O I Timer output[3:0] External timer clock input IO General input/output ports (some ports are output only) IO IO O SD receive/transmit data SD receive response/ transmit command SD clock IO IO IO I SPIMISO is the master data input line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. SPIMOSI is the master data output line, when SPI is configured as a master. When SPI is configured as a slave, these pins reverse its role. SPI clock SPI chip select(only for slave mode) IO IO DATA(-) for USB peripheral DATA(+) for USB peripheral IO IO DATA(-) from USB host DATA(+) from USB host O O O O Plus X-axis on-off control signal Minus X-axis on-off control signal Plus Y-axis on-off control signal Minus Y-axis on-off control signal IO O I IO O IIS-bus channel select clock IIS-bus serial data output IIS-bus serial data input IIS-bus serial clock CODEC system clock I/O Descriptions 1-22 S3C2410X PRODUCT OVERVIEW Table 1-3. S3C2410X Signal Descriptions (Sheet 4 of 5) Signal JTAG TEST LOGIC nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start. If debugger is used, A 10K pull-up resistor has to be connected. If debugger(black ICE) is not used, nTRST pin must be issued by a low active pulse(Typically connected to nRESET). TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's states. A 10K pull-up resistor has to be connected to TMS pin. TCK (TAP Controller Clock) provides the clock input for the JTAG logic. A 10K pull-up resistor must be connected to TCK pin. TDI (TAP Controller Data Input) is the serial input for test instructions and data. A 10K pull-up resistor must be connected to TDI pin. TDO (TAP Controller Data Output) is the serial output for test instructions and data. nRESET suspends any operation in progress and places S3C2410X into a known reset state. For a reset, nRESET must be held to L level for at least 4 FCLK after the processor power has been stabilized. For external device reset control(nRSTOUT = nRESET & nWDTRST & SW_RESET) 1.8V core power on-off control signal Probe for battery state(Does not wake up at power-off mode in case of low battery state). If it isn't used, it has to be High (3.3V). OM[3:2] determines how the clock is made. OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source. OM[3:2] = 01b, Crystal is used for MPLL CLK source and EXTCLK is used for UPLL CLK source. OM[3:2] = 10b, EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source. OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. EXTCLK I External clock source. When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only. When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only. If it isn't used, it has to be High (3.3V). Crystal Input for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, XTIpll has to be High (3.3V). Crystal Output for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, it has to be a floating pin. I/O Description TMS TCK TDI TDO nRESET I I I O ST Reset, Clock & Power nRSTOUT PWREN nBATT_FLT OM[3:2] O O I I XTIpll AI XTOpll AO 1-23 PRODUCT OVERVIEW S3C2410X Table 1-3. S3C2410X Signal Descriptions (Sheet 5 of 5) Signal MPLLCAP UPLLCAP XTIrtc XTOrtc CLKOUT[1:0] Power VDDalive VDDi/VDDiarm VSSi/VSSiarm VDDi_MPLL VSSi_MPLL VDDOP VDDMOP VSSMOP VSSOP RTCVDD VDDi_UPLL VSSi_UPLL VDDA_ADC VSSA_ADC P P P P P P P P P P P P P P S3C2410X reset block and port status register VDD(1.8V). It should be always supplied whether in normal mode or in power-off mode. S3C2410X core logic VDD(1.8V) for CPU. S3C2410X core logic VSS S3C2410X MPLL analog and digital VDD (1.8 V). S3C2410X MPLL analog and digital VSS. S3C2410X I/O port VDD(3.3V) S3C2410X Memory I/O VDD 3.3V : SCLK up to 100MHz S3C2410X Memory I/O VSS S3C2410X I/O port VSS RTC VDD (1.8 V, Not support 3.3V) (This pin must be connected to power properly if RTC isn't used) S3C2410X UPLL analog and digital VDD (1.8V) S3C2410X UPLL analog and digital VSS S3C2410X ADC VDD(3.3V) S3C2410X ADC VSS I/O AI AI AI AO O Loop filter capacitor for main clock. Loop filter capacitor for USB clock. 32.768 kHz crystal input for RTC. If it isn't used, it has to be High (1.8V). 32.768 kHz crystal output for RTC. If it isn't used, it has to be Float. Clock output signal. The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK. Description Reset, Clock & Power (continued) NOTES: 1. I/O means input/output. 2. AI/AO means analog input/analog output. 3. ST means schmitt-trigger. 4. P means power. 1-24 S3C2410X PRODUCT OVERVIEW S3C2410X SPECIAL REGISTERS Table 1-4. S3C2410X Special Registers (Sheet 1 of 11) Register Name BWSCON BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 BANKCON6 BANKCON7 REFRESH BANKSIZE MRSRB6 MRSRB7 Address (B. Endian) 0x48000000 0x48000004 0x48000008 0x4800000C 0x48000010 0x48000014 0x48000018 0x4800001C 0x48000020 0x48000024 0x48000028 0x4800002C 0x48000030 Address (L. Endian) Acc. Unit W Read/ Write R/W Function Memory Controller Bus Width & Wait Status Control Boot ROM Control BANK1 Control BANK2 Control BANK3 Control BANK4 Control BANK5 Control BANK6 Control BANK7 Control DRAM/SDRAM Refresh Control Flexible Bank Size Mode register set for SDRAM Mode register set for SDRAM 1-25 PRODUCT OVERVIEW S3C2410X Table 1-4. S3C2410X Special Registers (Sheet 2 of 11) Register Name USB Host Controller HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 Interrupt Controller SRCPND INTMOD INTMSK PRIORITY INTPND INTOFFSET SUBSRCPND INTSUBMSK 0X4A000000 0X4A000004 0X4A000008 0X4A00000C 0X4A000010 0X4A000014 0X4A000018 0X4A00001C W R/W W R/W W R/W R R/W R/W Interrupt Request Status Interrupt Mode Control Interrupt Mask Control IRQ Priority Control Interrupt Request Status Interrupt request source offset Sub source pending Interrupt sub mask 0x49000000 0x49000004 0x49000008 0x4900000C 0x49000010 0x49000014 0x49000018 0x4900001C 0x49000020 0x49000024 0x49000028 0x4900002C 0x49000030 0x49000034 0x49000038 0x4900003C 0x49000040 0x49000044 0x49000048 0x4900004C 0x49000050 0x49000054 0x49000058 Root Hub Group Frame Counter Group Memory Pointer Group Address (B. Endian) Address (L. Endian) Acc. Unit W Read/ Write Function Control and Status Group 1-26 S3C2410X PRODUCT OVERVIEW Table 1-4. S3C2410X Special Registers (Sheet 3 of 11) Register Name DMA DISRC0 DISRCC0 DIDST0 DIDSTC0 DCON0 DSTAT0 DCSRC0 DCDST0 DMASKTRIG0 DISRC1 DISRCC1 DIDST1 DIDSTC1 DCON1 DSTAT1 DCSRC1 DCDST1 DMASKTRIG1 DISRC2 DISRCC2 DIDST2 DIDSTC2 DCON2 DSTAT2 DCSRC2 DCDST2 DMASKTRIG2 DISRC3 DISRCC3 DIDST3 DIDSTC3 DCON3 DSTAT3 DCSRC3 DCDST3 DMASKTRIG3 0x4B000000 0x4B000004 0x4B000008 0x4B00000C 0x4B000010 0x4B000014 0x4B000018 0x4B00001C 0x4B000020 0x4B000040 0x4B000044 0x4B000048 0x4B00004C 0x4B000050 0x4B000054 0x4B000058 0x4B00005C 0x4B000060 0x4B000080 0x4B000084 0x4B000088 0x4B00008C 0x4B000090 0x4B000094 0x4B000098 0x4B00009C 0x4B0000A0 0x4B0000C0 0x4B0000C4 0x4B0000C8 0x4B0000CC 0x4B0000D0 0x4B0000D4 0x4B0000D8 0x4B0000DC 0x4B0000E0 R/W R Address (B. Endian) Address (L. Endian) Acc. Unit W Read/ Write R/W Function DMA 0 Initial Source DMA 0 Initial Source Control DMA 0 Initial Destination DMA 0 Initial Destination Control DMA 0 Control R DMA 0 Count DMA 0 Current Source DMA 0 Current Destination W R/W DMA 0 Mask Trigger DMA 1 Initial Source DMA 1 Initial Source Control DMA 1 Initial Destination DMA 1 Initial Destination Control DMA 1 Control R W R/W DMA 1 Count DMA 1 Current Source DMA 1 Current Destination DMA 1 Mask Trigger DMA 2 Initial Source DMA 2 Initial Source Control DMA 2 Initial Destination DMA 2 Initial Destination Control DMA 2 Control R W R/W W R/W DMA 2 Count DMA 2 Current Source DMA 2 Current Destination DMA 2 Mask Trigger DMA 3 Initial Source DMA 3 Initial Source Control DMA 3 Initial Destination DMA 3 Initial Destination Control DMA 3 Control DMA 3 Count DMA 3 Current Source DMA 3 Current Destination DMA 3 Mask Trigger 1-27 PRODUCT OVERVIEW S3C2410X Table 1-4. S3C2410X Special Registers (Sheet 4 of 11) Register Name LOCKTIME MPLLCON UPLLCON CLKCON CLKSLOW CLKDIVN LCD Controller LCDCON1 LCDCON2 LCDCON3 LCDCON4 LCDCON5 LCDSADDR1 LCDSADDR2 LCDSADDR3 REDLUT GREENLUT BLUELUT DITHMODE TPAL LCDINTPND LCDSRCPND LCDINTMSK LPCSEL NAND Flash NFCONF NFCMD NFADDR NFDATA NFSTAT NFECC 0x4E000000 0x4E000004 0x4E000008 0x4E00000C 0x4E000010 0x4E000014 R R/W Address (B. Endian) 0x4C000000 0x4C000004 0x4C000008 0x4C00000C 0x4C000010 0x4C000014 0X4D000000 0X4D000004 0X4D000008 0X4D00000C 0X4D000010 0X4D000014 0X4D000018 0X4D00001C 0X4D000020 0X4D000024 0X4D000028 0X4D00004C 0X4D000050 0X4D000054 0X4D000058 0X4D00005C 0X4D000060 Address (L. Endian) Acc. Unit W Read/ Write R/W Function Clock & Power Management PLL Lock Time Counter MPLL Control UPLL Control Clock Generator Control Slow Clock Control Clock divider Control W R/W LCD Control 1 LCD Control 2 LCD Control 3 LCD Control 4 LCD Control 5 STN/TFT: Frame Buffer Start Address1 STN/TFT: Frame Buffer Start Address2 STN/TFT: Virtual Screen Address Set STN: Red Lookup Table STN: Green Lookup Table STN: Blue Lookup Table STN: Dithering Mode TFT: Temporary Palette LCD Interrupt Pending LCD Interrupt Source LCD Interrupt Mask LPC3600 Control W R/W NAND Flash Configuration NAND Flash Command NAND Flash Address NAND Flash Data NAND Flash Operation Status NAND Flash ECC 1-28 S3C2410X PRODUCT OVERVIEW Table 1-4. S3C2410X Special Registers (Sheet 5 of 11) Register Name UART ULCON0 UCON0 UFCON0 UMCON0 UTRSTAT0 UERSTAT0 UFSTAT0 UMSTAT0 UTXH0 URXH0 UBRDIV0 ULCON1 UCON1 UFCON1 UMCON1 UTRSTAT1 UERSTAT1 UFSTAT1 UMSTAT1 UTXH1 URXH1 UBRDIV1 ULCON2 UCON2 UFCON2 UTRSTAT2 UERSTAT2 UFSTAT2 UTXH2 URXH2 UBRDIV2 0x50000000 0x50000004 0x50000008 0x5000000C 0x50000010 0x50000014 0x50000018 0x5000001C 0x50000023 0x50000027 0x50000028 0x50004000 0x50004004 0x50004008 0x5000400C 0x50004010 0x50004014 0x50004018 0x5000401C 0x50004023 0x50004027 0x50004028 0x50008000 0x50008004 0x50008008 0x50008010 0x50008014 0x50008018 0x50008023 0x50008027 0x50008028 0x50008020 0x50008024 Address (B. Endian) Address (L. Endian) Acc. Unit W Read/ Write R/W Function UART 0 Line Control UART 0 Control UART 0 FIFO Control UART 0 Modem Control R UART 0 Tx/Rx Status UART 0 Rx Error Status UART 0 FIFO Status UART 0 Modem Status 0x50000020 0x50000024 B W W W R R/W R/W UART 0 Transmission Hold UART 0 Receive Buffer UART 0 Baud Rate Divisor UART 1 Line Control UART 1 Control UART 1 FIFO Control UART 1 Modem Control R UART 1 Tx/Rx Status UART 1 Rx Error Status UART 1 FIFO Status UART 1 Modem Status 0x50004020 0x50004024 B W W W R R/W R/W UART 1 Transmission Hold UART 1 Receive Buffer UART 1 Baud Rate Divisor UART 2 Line Control UART 2 Control UART 2 FIFO Control R UART 2 Tx/Rx Status UART 2 Rx Error Status UART 2 FIFO Status B W W R R/W UART 2 Transmission Hold UART 2 Receive Buffer UART 2 Baud Rate Divisor 1-29 PRODUCT OVERVIEW S3C2410X Table 1-4. S3C2410X Special Registers (Sheet 6 of 11) Register Name PWM Timer TCFG0 TCFG1 TCON TCNTB0 TCMPB0 TCNTO0 TCNTB1 TCMPB1 TCNTO1 TCNTB2 TCMPB2 TCNTO2 TCNTB3 TCMPB3 TCNTO3 TCNTB4 TCNTO4 0x51000000 0x51000004 0x51000008 0x5100000C 0x51000010 0x51000014 0x51000018 0x5100001C 0x51000020 0x51000024 0x51000028 0x5100002C 0x51000030 0x51000034 0x51000038 0x5100003C 0x51000040 R R/W R R R/W R R/W R R/W Address (B. Endian) Address (L. Endian) Acc. Unit W Read/ Write R/W Function Timer Configuration Timer Configuration Timer Control Timer Count Buffer 0 Timer Compare Buffer 0 Timer Count Observation 0 Timer Count Buffer 1 Timer Compare Buffer 1 Timer Count Observation 1 Timer Count Buffer 2 Timer Compare Buffer 2 Timer Count Observation 2 Timer Count Buffer 3 Timer Compare Buffer 3 Timer Count Observation 3 Timer Count Buffer 4 Timer Count Observation 4 1-30 S3C2410X PRODUCT OVERVIEW Table 1-4. S3C2410X Special Registers (Sheet 7 of 11) Register Name USB Device FUNC_ADDR_REG PWR_REG EP_INT_REG USB_INT_REG EP_INT_EN_REG USB_INT_EN_REG FRAME_NUM1_REG INDEX_REG EP0_CSR IN_CSR1_REG IN_CSR2_REG MAXP_REG OUT_CSR1_REG OUT_CSR2_REG OUT_FIFO_CNT1_REG OUT_FIFO_CNT2_REG EP0_FIFO EP1_FIFO EP2_FIFO EP3_FIFO EP4_FIFO EP1_DMA_CON EP1_DMA_UNIT EP1_DMA_FIFO EP1_DMA_TX_LO EP1_DMA_TX_MD EP1_DMA_TX_HI 0x52000143 0x52000147 0x5200014B 0x5200015B 0x5200015F 0x5200016F 0x52000173 0x5200017B 0x52000187 0x52000187 0x5200018B 0x5200018F 0x52000193 0x52000197 0x5200019B 0x5200019F 0x520001C3 0x520001C7 0x520001CB 0x520001CF 0x520001D3 0x52000203 0x52000207 0x5200020B 0x5200020F 0x52000213 0x52000217 0x52000140 0x52000144 0x52000148 0x52000158 0x5200015C 0x5200016C 0x52000170 0x52000178 0x52000184 0x52000184 0x52000188 0x5200018C 0x52000190 0x52000194 0x52000198 0x5200019C 0x520001C0 0x520001C4 0x520001C8 0x520001CC 0x520001D0 0x52000200 0x52000204 0x52000208 0x5200020C 0x52000210 0x52000214 R/W R R R/W B R/W Function Address Power Management EP Interrupt Pending and Clear USB Interrupt Pending and Clear Interrupt Enable Interrupt Enable Frame Number Lower Byte Register Index Endpoint 0 Status In Endpoint Control Status In Endpoint Control Status Endpoint Max Packet Out Endpoint Control Status Out Endpoint Control Status Endpoint Out Write Count Endpoint Out Write Count Endpoint 0 FIFO Endpoint 1 FIFO Endpoint 2 FIFO Endpoint 3 FIFO Endpoint 4 FIFO EP1 DMA Interface Control EP1 DMA Tx Unit Counter EP1 DMA Tx FIFO Counter EP1 DMA Total Tx Counter EP1 DMA Total Tx Counter EP1 DMA Total Tx Counter Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function 1-31 PRODUCT OVERVIEW S3C2410X Table 1-4. S3C2410X Special Registers (Sheet 8 of 11)) Register Name USB Device (Continued) EP2_DMA_CON EP2_DMA_UNIT EP2_DMA_FIFO EP2_DMA_TX_LO EP2_DMA_TX_MD EP2_DMA_TX_HI EP3_DMA_CON EP3_DMA_UNIT EP3_DMA_FIFO EP3_DMA_TX_LO EP3_DMA_TX_MD EP3_DMA_TX_HI EP4_DMA_CON EP4_DMA_UNIT EP4_DMA_FIFO EP4_DMA_TX_LO EP4_DMA_TX_MD EP4_DMA_TX_HI Watchdog Timer WTCON WTDAT WTCNT IIC IICCON IICSTAT IICADD IICDS IIS IISCON IISMOD IISPSR IISFCON IISFIFO 0x55000000,02 0x55000000 0x55000004,06 0x55000004 0x55000008,0A 0x55000008 0x5500000C,0E 0x5500000C 0x55000012 0x55000010 HW,W HW,W HW,W HW,W HW R/W IIS Control IIS Mode IIS Prescaler IIS FIFO Control IIS FIFO Entry 0x54000000 0x54000004 0x54000008 0x5400000C Address (B. Endian) 0x5200021B 0x5200021F 0x52000223 0x52000227 0x5200022B 0x5200022F 0x52000243 0x52000247 0x5200024B 0x5200024F 0x52000253 0x52000257 0x5200025B 0x5200025F 0x52000263 0x52000267 0x5200026B 0x5200026F 0x53000000 0x53000004 0x53000008 Address (L. Endian) 0x52000218 0x5200021C 0x52000220 0x52000224 0x52000228 0x5200022C 0x52000240 0x52000244 0x52000248 0x5200024C 0x52000250 0x52000254 0x52000258 0x5200025C 0x52000260 0x52000264 0x52000268 0x5200026C Acc. Unit B Read/W rite R/W Function EP2 DMA Interface Control EP2 DMA Tx Unit Counter EP2 DMA Tx FIFO Counter EP2 DMA Total Tx Counter EP2 DMA Total Tx Counter EP2 DMA Total Tx Counter EP3 DMA Interface Control EP3 DMA Tx Unit Counter EP3 DMA Tx FIFO Counter EP3 DMA Total Tx Counter EP3 DMA Total Tx Counter EP3 DMA Total Tx Counter EP4 DMA Interface Control EP4 DMA Tx Unit Counter EP4 DMA Tx FIFO Counter EP4 DMA Total Tx Counter EP4 DMA Total Tx Counter EP4 DMA Total Tx Counter W R/W Watchdog Timer Mode Watchdog Timer Data Watchdog Timer Count W R/W IIC Control IIC Status IIC Address IIC Data Shift 1-32 S3C2410X PRODUCT OVERVIEW Table 1-4. S3C2410X Special Registers (Sheet 9 of 11) Register Name I/O port GPACON GPADAT GPBCON GPBDAT GPBUP GPCCON GPCDAT GPCUP GPDCON GPDDA1T GPDUP GPECON GPEDAT GPEUP GPFCON GPFDAT GPFUP GPGCON GPGDAT GPGUP GPHCON GPHDAT GPHUP MISCCR DCLKCON EXTINT0 EXTINT1 EXTINT2 EINTFLT0 EINTFLT1 EINTFLT2 EINTFLT3 EINTMASK EINTPEND GSTATUS0 GSTATUS1 0x56000000 0x56000004 0x56000010 0x56000014 0x56000018 0x56000020 0x56000024 0x56000028 0x56000030 0x56000034 0x56000038 0x56000040 0x56000044 0x56000048 0x56000050 0x56000054 0x56000058 0x56000060 0x56000064 0x56000068 0x56000070 0x56000074 0x56000078 0x56000080 0x56000084 0x56000088 0x5600008C 0x56000090 0x56000094 0x56000098 0x5600009C 0x560000A0 0x560000A4 0x560000A8 0x560000AC 0x560000B0 Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function W R/W Port A Control Port A Data Port B Control Port B Data Pull-up Control B Port C Control Port C Data Pull-up Control C Port D Control Port D Data Pull-up Control D Port E Control Port E Data Pull-up Control E Port F Control Port F Data Pull-up Control F Port G Control Port G Data Pull-up Control G Port H Control Port H Data Pull-up Control H W R/W Miscellaneous Control DCLK0/1 Control External Interrupt Control Register 0 External Interrupt Control Register 1 External Interrupt Control Register 2 Reserved Reserved External Interrupt Filter Control Register 2 External Interrupt Filter Control Register 3 External Interrupt Mask External Interrupt Pending External Pin Status External Pin Status 1-33 PRODUCT OVERVIEW S3C2410X Table 1-4. S3C2410X Special Registers (Sheet 10 of 11) Register Name RTC RTCCON TICNT RTCALM ALMSEC ALMMIN ALMHOUR ALMDATE ALMMON ALMYEAR RTCRST BCDSEC BCDMIN BCDHOUR BCDDATE BCDDAY BCDMON BCDYEAR A/D converter ADCCON ADCTSC ADCDLY ADCDAT0 ADCDAT1 SPI SPCON0,1 SPSTA0,1 SPPIN0,1 SPPRE0,1 SPTDAT0,1 SPRDAT0,1 0x59000000,20 0x59000004,24 0x59000008,28 0x5900000C,2C 0x59000010,30 0x59000014,34 R Address (B. Endian) 0x57000043 0x57000047 0x57000053 0x57000057 0x5700005B 0x5700005F 0x57000063 0x57000067 0x5700006B 0x5700006F 0x57000073 0x57000077 0x5700007B 0x5700007F 0x57000083 0x57000087 0x5700008B 0x58000000 0x58000004 0x58000008 0x5800000C 0x58000010 Address (L. Endian) 0x57000040 0x57000044 0x57000050 0x57000054 0x57000058 0x5700005C 0x57000060 0x57000064 0x57000068 0x5700006C 0x57000070 0x57000074 0x57000078 0x5700007C 0x57000080 0x57000084 0x57000088 Acc. Unit B Read/ Write R/W RTC Control Function Tick time count RTC Alarm Control Alarm Second Alarm Minute Alarm Hour Alarm Day Alarm Month Alarm Year RTC Round Reset BCD Second BCD Minute BCD Hour BCD Day BCD Date BCD Month BCD Year W R/W ADC Control ADC Touch Screen Control ADC Start or Interval Delay R ADC Conversion Data ADC Conversion Data W R/W R R/W SPI Control SPI Status SPI Pin Control SPI Baud Rate Prescaler SPI Tx Data SPI Rx Data 1-34 S3C2410X PRODUCT OVERVIEW Table 1-4. S3C2410X Special Registers (Sheet 11 of 11) Register Name SD interface SDICON SDIPRE SDICmdArg SDICmdCon SDICmdSta SDIRSP0 SDIRSP1 SDIRSP2 SDIRSP3 SDIDTimer SDIBSize SDIDatCon SDIDatCnt SDIDatSta SDIFSTA SDIDAT SDIIntMsk 0x5A000000 0x5A000004 0x5A000008 0x5A00000C 0x5A000010 0x5A000014 0x5A000018 0x5A00001C 0x5A000020 0x5A000024 0x5A000028 0x5A00002C 0x5A000030 0x5A000034 0x5A000038 0x5A00003F 0x5A000040 0x5A00003C Address (B. Endian) Address (L. Endian) Acc. Unit W Read/ Write R/W Function SDI Control SDI Baud Rate Prescaler SDI Command Argument SDI Command Control R/(C) R SDI Command Status SDI Response SDI Response SDI Response SDI Response R/W SDI Data / Busy Timer SDI Block Size SDI Data control R R/(C) R B W R/W SDI Data Remain Counter SDI Data Status SDI FIFO Status SDI Data SDI Interrupt Mask 1-35 PRODUCT OVERVIEW S3C2410X Cautions on S3C2410X Special Registers 1. In the little endian mode, L. endian address must be used. In the big endian mode, B. endian address must be used. 2. The special registers have to be accessed for each recommended access unit. 3. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit) at little/big endian. 4. Make sure that the ADC registers, RTC registers and UART registers be read/written by the specified access unit and the specified address. Moreover, one must carefully consider which endian mode is used. 5. W : 32-bit register, which must be accessed by LDR/STR or int type pointer(int *). HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *). B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char int *). 1-36 S3C2410X PROGRAMMER'S MODEL 2 OVERVIEW * * PROGRAMMER'S MODEL S3C2410X has been developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines, Ltd. PROCESSOR OPERATING STATES From the programmer's point of view, the ARM920T can be in one of two states: ARM state which executes 32-bit, word-aligned ARM instructions. THUMB state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1 to select between alternate halfwords. NOTES Transition between these two states does not affect the processor mode or the contents of the registers. SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand register. Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the processor in THUMB state. Entering ARM State Entry into ARM state happens: * * On execution of the BX instruction with the state bit clear in the operand register. On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is placed in the exception mode's link register, and execution commences at the exception's vector address. MEMORY FORMATS ARM920T views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM920T can treat words in memory as being stored either in Big-Endian or Little-Endian format. 2-1 PROGRAMMER'S MODEL S3C2410X BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24. Higher Address 31 8 4 0 Lower Address 24 23 9 5 1 16 15 10 6 2 8 7 11 7 3 0 Word Address 8 4 0 Most significant byte is at lowest address. Word is addressed by byte address of most significant byte. Figure 2-1. Big-Endian Addresses of Bytes within Words LITTLE-ENDIAN FORMAT In Little-Endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0. Higher Address 31 11 7 3 Lower Address 24 23 10 6 2 16 15 9 5 1 8 7 8 4 0 0 Word Address 8 4 0 Least significant byte is at lowest address. Word is addressed by byte address of least significant byte. Figure 2-2. Little-Endian Addresses of Bytes within Words INSTRUCTION LENGTH Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). Data Types ARM920T supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to fourbyte boundaries and half words to two-byte boundaries. 2-2 S3C2410X PROGRAMMER'S MODEL OPERATING MODES ARM920T supports seven modes of operation: * * * * * * * User (usr): The normal ARM program execution state FIQ (fiq): Designed to support a data transfer or channel process IRQ (irq): Used for general-purpose interrupt handling Supervisor (svc): Protected mode for the operating system Abort mode (abt): Entered after a data or instruction prefetch abort System (sys): A privileged user mode for the operating system Undefined (und): Entered when an undefined instruction is executed Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes' known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources. REGISTERS ARM920T has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer. The ARM State Register Set In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (nonUser) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle. The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information. Register 14 is used as the subroutine link register. This receives a copy of R15 when a Branch and Link (BL) instruction is executed. At all other times it may be treated as a general-purpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when Branch and Link instructions are executed within interrupt or exception routines. holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC. is the CPSR (Current Program Status Register). This contains condition code flags and the current mode bits. Register 15 Register 16 FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers. 2-3 PROGRAMMER'S MODEL S3C2410X ARM State General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) FIQ R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC) Supervisor R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC) Abort R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC) IRQ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC) Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC) ARM State Program Status Registers CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und = banked register Figure 2-3. Register Organization in ARM State 2-4 S3C2410X PROGRAMMER'S MODEL The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4. THUMB State General Registers and Program Counter System & User R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC FIQ R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC Supervisor R0 R1 R2 R3 R4 R5 R6 R7 SP_svc LR_svc PC Abort R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt PC IRQ R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC Undefined R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC THUMB State Program Status Registers CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und = banked register Figure 2-4. Register Organization in THUMB state 2-5 PROGRAMMER'S MODEL S3C2410X The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way: * * * * * THUMB state R0-R7 and ARM state R0-R7 are identical THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical THUMB state SP maps onto ARM state R13 THUMB state LR maps onto ARM state R14 The THUMB state Program Counter maps onto the ARM state Program Counter (R15) This relationship is shown in Figure 2-5. THUMB state R0 R1 R2 R3 R4 R5 R6 R7 ARM state R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Stack Pointer (R13) Link register (R14) Program Counter (R15) CPSR SPSR Stack Pointer (SP) Link register (LR) Program Counter (PC) CPSR SPSR Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers 2-6 Hi-registers Lo-registers S3C2410X PROGRAMMER'S MODEL Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage. A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register, and from a Hi register to a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions. For more information, refer to Figure 3-34. THE PROGRAM STATUS REGISTERS The ARM920T contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These register's functions are: * * * Hold information about the most recently performed ALU operation Control the enabling and disabling of interrupts Set the processor operating mode The arrangement of bits is shown in Figure 2-6. Condition Code Flags 31 N 30 Z 29 C 28 V 27 26 (Reserved) 25 24 23 ~ ~ I ~ ~ Overflow Carry/Borrow/Extend Zero Negative/Less Than F T 8 7 6 5 Control Bits 4 M4 3 M3 2 M2 1 M1 0 M0 Mode bits State bit FIQ disable IRQ disable Figure 2-6. Program Status Register Format 2-7 PROGRAMMER'S MODEL S3C2410X The Condition Code Flags The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details. The Control Bits The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will be changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software. The T bit This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal. Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state. Interrupt disable bits The mode bits The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively. The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor's operating mode, as shown in Table 2-1. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied. The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero. Reserved bits 2-8 S3C2410X PROGRAMMER'S MODEL Table 2-1. PSR Mode Bit Values M[4:0] 10000 User Mode Visible THUMB state registers R7..R0, LR, SP PC, CPSR R7..R0, LR_fiq, SP_fiq PC, CPSR, SPSR_fiq R7..R0, LR_irq, SP_irq PC, CPSR, SPSR_irq R7..R0, LR_svc, SP_svc, PC, CPSR, SPSR_svc R7..R0, LR_abt, SP_abt, PC, CPSR, SPSR_abt R7..R0 LR_und, SP_und, PC, CPSR, SPSR_und R7..R0, LR, SP PC, CPSR Visible ARM state registers R14..R0, PC, CPSR R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq R12..R0, R14_irq, R13_irq, PC, CPSR, SPSR_irq R12..R0, R14_svc, R13_svc, PC, CPSR, SPSR_svc R12..R0, R14_abt, R13_abt, PC, CPSR, SPSR_abt R12..R0, R14_und, R13_und, PC, CPSR R14..R0, PC, CPSR 10001 FIQ 10010 IRQ 10011 Supervisor 10111 Abort 11011 Undefined 11111 System Reserved bits The remaining bits in the PSR's are reserved. When changing a PSR's flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero. 2-9 PROGRAMMER'S MODEL S3C2410X EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order. See Exception Priorities on page 2-14. Action on Entering an Exception When handling an exception, the ARM920T: 1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from THUMB state, then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception. This means that the exception handler need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC, R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state. 2. Copies the CPSR into the appropriate SPSR 3. Forces the CPSR mode bits to a value which depends on the exception 4. Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions. If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the PC is loaded with the exception vector address. Action on Leaving an Exception On completion, the exception handler: 1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the type of exception.) 2. Copies the SPSR back to the CPSR 3. Clears the interrupt disable flags, if they were set on entry NOTES An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception. 2-10 S3C2410X PROGRAMMER'S MODEL Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table 2-2. Exception Entry/Exit Return Instruction BL SWI UDEF FIQ IRQ PABT DABT RESET MOV PC, R14 MOVS PC, R14_svc MOVS PC, R14_und SUBS PC, R14_fiq, #4 SUBS PC, R14_irq, #4 SUBS PC, R14_abt, #4 SUBS PC, R14_abt, #8 NA PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 PC + 4 PC + 8 - Previous State ARM R14_x THUMB R14_x PC + 2 PC + 2 PC + 2 PC + 4 PC + 4 PC + 4 PC + 8 - 1 1 1 2 2 1 3 4 Notes NOTES: 1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort. 2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority. 3. Where PC is the address of the Load or Store instruction which generated the data abort. 4. The value saved in R14_svc upon reset is unpredictable. FIQ The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context switching). FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow. Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt by executing SUBS PC,R14_fiq,#4 FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is clear, ARM920T checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction. 2-11 PROGRAMMER'S MODEL S3C2410X IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode. Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the interrupt by executing SUBS Abort An abort indicates that the current memory access cannot be completed. It can be signaled by the external ABORT input. ARM920T checks for the abort exception during memory access cycles. There are two types of abort: * * Prefetch abort: occurs during an instruction prefetch. Data abort: occurs during a data access. PC,R14_irq,#4 If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. If the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place. If a data abort occurs, the action taken depends on the instruction type: * * * Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be aware of this. The swap instruction (SWP) is aborted as though it had not been executed. Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last register to be transferred) is preserved in an aborted LDM instruction. The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. The application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort. After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb): SUBS SUBS PC,R14_abt,#4 PC,R14_abt,#8 ; for a prefetch abort, or ; for a data abort This restores both the PC and the CPSR, and retries the aborted instruction. 2-12 S3C2410X PROGRAMMER'S MODEL Software Interrupt The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): MOV PC,R14_svc This restores the PC and CPSR, and returns to the instruction following the SWI. NOTES nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM920T CPU core. Undefined Instruction When ARM920T comes across an instruction which it cannot handle, it takes the undefined instruction trap. This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation. After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or Thumb): MOVS PC,R14_und This restores the CPSR and returns to the instruction following the undefined instruction. Exception Vectors The following table shows the exception vector addresses. Table 2-3. Exception Vectors Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C Reset Undefined instruction Software Interrupt Abort (prefetch) Abort (data) Reserved IRQ FIQ Exception Supervisor Undefined Supervisor Abort Abort Reserved IRQ FIQ Mode in Entry 2-13 PROGRAMMER'S MODEL S3C2410X Exception Priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6. Undefined Instruction, Software interrupt. Not All Exceptions Can Occur at Once: Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decodings of the current instruction. If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM920T enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations. 2-14 S3C2410X PROGRAMMER'S MODEL INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM920T will be executing the instruction at 0x1C. Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchronizer (Tsyncmin) plus Tfiq. This is 4 processor cycles. RESET When the nRESET signal goes LOW, ARM920T abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. When nRESET goes HIGH again, ARM920T: 1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined. 2. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit. 3. Forces the PC to fetch the next instruction from address 0x00. 4. Execution resumes in ARM state. 2-15 PROGRAMMER'S MODEL S3C2410X NOTES 2-16 S3C2410X ARM INSTRUCTION SET 3 ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core. FORMAT SUMMARY The ARM instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond 00I Opcode S Rn Rd RdHi Rn Rd Rn RdLo Rd Operand2 Rs Rn 1001 1001 Rm Rm Rm Rn Rm Offset Data/Processing/ PSR Transfer Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer: register offset Halfword Data Transfer: immendiate offset Single Data Transfer 1 Rn Offset Rn CRn CRn CRd CRd Rd CP# CP# CP# CP CP Offset 0 1 CRm CRm Register List Undefined Block Data Transfer Branch Coprocessor Data Transfer Coprocessor Data Operation Coprocessor Register Transfer Software Interrupt 0 00000AS 0 0 00 1UAS 0 0010B00 00001001 000100101111111111110001 0 0 0 PU0WL 0 0 0 PU1WL 0 1 I P U BWL 01I 1 0 0 P U BWL 101L 1 1 0 P U BWL 1110 1110 1111 CP Opc CP Opc L Rn Rn Rn Rd Rd Rd 00001SH1 Offset 1SH1 Offset Ignored by processor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 3-1. ARM Instruction Set Format 3-1 ARM INSTRUCTION SET S3C2410X NOTES Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations. INSTRUCTION SUMMARY Table 3-1. The ARM Instruction Set Mnemonic ADC ADD AND B BIC BL BX CDP CMN CMP EOR LDC LDM LDR MCR MLA MOV Add with carry Add AND Branch Bit Clear Branch with Link Branch and Exchange Coprocessor Data Processing Compare Negative Compare Exclusive OR Load coprocessor from memory Load multiple registers Load register from memory Move CPU register to coprocessor register Multiply Accumulate Move register or constant Instruction Rd: = Rn + Op2 Rd: = Rn AND Op2 R15: = address Rd: = Rn AND NOT Op2 R14: = R15, R15: = address R15: = Rn, T bit: = Rn[0] (Coprocessor-specific) CPSR flags: = Rn + Op2 CPSR flags: = Rn - Op2 Rd: = (Rn AND NOT Op2) OR (Op2 AND NOT Rn) Coprocessor load Stack manipulation (Pop) Rd: = (address) cRn: = rRn { 3-2 S3C2410X ARM INSTRUCTION SET Table 3-1. The ARM Instruction Set (Continued) Mnemonic MRC MRS MSR MUL MVN ORR RSB RSC SBC STC STM STR SUB SWI SWP TEQ TST Instruction Move from coprocessor register to CPU register Move PSR status/flags to register Move register to PSR status/flags Multiply Move negative register OR Reverse Subtract Reverse Subtract with Carry Subtract with Carry Store coprocessor register to memory Store Multiple Store register to memory Subtract Software Interrupt Swap register with memory Test bitwise equality Test bits Action Rn: = cRn { 3-3 ARM INSTRUCTION SET S3C2410X THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which means the Branch will only be taken if the Z flag is set. In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved, and must not be used. In the absence of a suffix, the condition field of most instructions is set to "Always" (suffix AL). This means the instruction will always be executed regardless of the CPSR condition codes. Table 3-2. Condition Code Summary Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Suffix EQ NE CS CC MI PL VS VC HI LS GE LT GT LE AL Z set Z clear C set C clear N set N clear V set V clear C set and Z clear C clear or Z set N equals V N not equal to V Z clear AND (N equals V) Z set OR (N not equal to V) (ignored) Flags equal not equal unsigned higher or same unsigned lower negative positive or zero overflow no overflow unsigned higher unsigned lower or same greater or equal less than greater than less than or equal always Meaning 3-4 S3C2410X ARM INSTRUCTION SET BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the instruction stream will be decoded as ARM or THUMB instructions. 31 Cond 28 27 24 23 20 19 16 15 12 11 87 43 Rn 0 000100101111111111110001 [3:0] Operand Register If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions If bit0 of Rn =0, subsequent instructions decoded as ARM instructions [31:28] Condition Field Figure 3-2. Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and nonsequential (N-cycle), respectively. ASSEMBLER SYNTAX BX - branch and exchange. BX {cond} Rn {cond} Rn Two character condition mnemonic. See Table 3-2. is an expression evaluating to a valid register number. USING R15 AS AN OPERAND If R15 is used as an operand, the behavior is undefined. 3-5 ARM INSTRUCTION SET S3C2410X Examples ADR R0, Into_THUMB + 1 ; ; ; ; ; ; ; Generate branch target address and set bit 0 high - hence arrive in THUMB state. Branch and change to THUMB state. Assemble subsequent code as THUMB instructions BX CODE16 Into_THUMB * * * R0 ADR R5, Back_to_ARM BX R5 * * * ; Generate branch target to word aligned address ; - hence bit 0 is low and so change back to ARM state. ; Branch and change back to ARM state. ALIGN CODE32 Back_to_ARM ; Word align ; Assemble subsequent code as ARM instructions 3-6 S3C2410X ARM INSTRUCTION SET BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. 31 Cond 28 27 101 25 24 23 L Offset 0 [24] Link bit 0 = Branch 1 = Branch with link [31:28] Condition Field Figure 3-3. Branch Instructions Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction. Branches beyond +/- 32Mbytes must use an offset or absolute destination which has been previously loaded into a register. In this case the PC should be manually saved in R14 if a Branch with Link type operation is required. THE LINK BIT Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the PC and R14[1:0] are always cleared. To return from a routine called by Branch with Link use MOV PC,R14 if the link register is still valid or LDM Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn. INSTRUCTION CYCLE TIMES Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S and N are defined as sequential (S-cycle) and internal (I-cycle). 3-7 ARM INSTRUCTION SET S3C2410X ASSEMBLER SYNTAX Items in {} are optional. Items in <> must be present. B{L}{cond} 3-8 S3C2410X ARM INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4. 31 Cond 28 27 26 25 24 00 L 21 20 19 S Rn 16 15 Rd 12 11 Operand2 0 OpCode [15:12] Destination register 0 = Branch 1 = Branch with link [19:16] 1st operand register 0 = Branch 1 = Branch with link [20] Set condition codes 0 = Do not after condition codes 1 = Set condition codes [24:21] Operation codes 0000 = AND-Rd: = Op1 AND Op2 0001 = EOR-Rd: = Op1 EOR Op2 0010 = SUB-Rd: = Op1-Op2 0011 = RSB-Rd: = Op2-Op1 0100 = ADD-Rd: = Op1+Op2 0101 = ADC-Rd: = Op1+Op2+C 0110 = SBC-Rd: = OP1-Op2+C-1 0111 = RSC-Rd: = Op2-Op1+C-1 1000 = TST-set condition codes on Op1 AND Op2 1001 = TEO-set condition codes on OP1 EOR Op2 1010 = CMP-set condition codes on Op1-Op2 1011 = SMN-set condition codes on Op1+Op2 1100 = ORR-Rd: = Op1 OR Op2 1101 = MOV-Rd: =Op2 1110 = BIC-Rd: = Op1 AND NOT Op2 1111 = MVN-Rd: = NOT Op2 [25] Immediate operand 0 = Operand 2 is a register 1 = Operand 2 is an immediate value [11:0] Operand 2 type selection 11 Shift [3:0] 2nd operand register 11 Rotate 87 Imm [11:8] Shift applied to Imm 0 34 Rm [11:4] Shift applied to Rm 0 [7:0] Unsigned 8 bit immediate value [31:28] Condition field Figure 3-4. Data Processing Instructions 3-9 ARM INSTRUCTION SET S3C2410X The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the S bit in the instruction. Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in Table 3-3. 3-10 S3C2410X ARM INSTRUCTION SET CPSR FLAGS The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result. Table 3-3. ARM Data Processing Instructions Assembler Mnemonic AND EOR WUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN OP Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Action Operand1 AND operand2 Operand1 EOR operand2 Operand1 - operand2 Operand2 operand1 Operand1 + operand2 Operand1 + operand2 + carry Operand1 - operand2 + carry - 1 Operand2 - operand1 + carry - 1 As AND, but result is not written As EOR, but result is not written As SUB, but result is not written As ADD, but result is not written Operand1 OR operand2 Operand2 (operand1 is ignored) Operand1 AND NOT operand2 (Bit clear) NOT operand2 (operand1 is ignored) The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed). 3-11 ARM INSTRUCTION SET S3C2410X SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than R15). The encoding for the different shift types is shown in Figure 3-5. 11 7654 0 11 RS 87654 0 1 [6:5] Shift type 00 = logical left 10 = arithmetic right 01 = logical right 11 = rotate right [6:5] Shift type 00 = logical left 10 = arithmetic right 01 = logical right 11 = rotate right [11:7] Shift amount 5 bit unsigned integer [11:8] Shift register Shift amount specified in bottom-byte of Rs Figure 3-5. ARM Shift Operations Instruction specified shift amount When the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. A logical shift left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class (see above). For example, the effect of LSL #5 is shown in Figure 3-6. 31 27 26 Contents of Rm 0 carry out Value of Operand 2 00000 Figure 3-6. Logical Shift Left NOTES LSL #0 is a special case, where the shifter carry out is the old value of the CPSR C flag. The contents of Rm are used directly as the second operand. A logical shift right (LSR) is similar, but the contents of Rm are moved to less significant positions in the result. LSR #5 has the effect shown in Figure 3-7. 3-12 S3C2410X ARM INSTRUCTION SET 31 Contents of Rm 54 0 carry out 00000 Value of Operand 2 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified. An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown in Figure 3-8. 31 30 Contents of Rm 54 0 carry out Value of Operand 2 Figure 3-8. Arithmetic Shift Right The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to the value of bit 31 of Rm. 3-13 ARM INSTRUCTION SET S3C2410X Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9. 31 Contents of Rm 54 0 carry out Value of Operand 2 Figure 3-9. Rotate Right The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3-10. 31 Contents of Rm 10 C in Value of Operand 2 carry out Figure 3-10. Rotate Right Extended 3-14 S3C2410X ARM INSTRUCTION SET Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output. If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. If the value in the byte is 32 or more, the result will be a logical extension of the shift described above: 1. LSL by 32 has result zero, carry out equal to bit 0 of Rm. 2. LSL by more than 32 has result zero, carry out zero. 3. LSR by 32 has result zero, carry out equal to bit 31 of Rm. 4. LSR by more than 32 has result zero, carry out zero. 5. ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm. 6. ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm. 7. ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above. NOTES The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction. 3-15 ARM INSTRUCTION SET S3C2410X IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. This enables many common constants to be generated, for example all powers of 2. WRITING TO R15 When Rd is a register other than R15, the condition code flags in the CPSR may be updated from the ALU flags as described above. When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected. When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR. This allows state changes which atomically restore both PC and CPSR. This form of instruction should not be used in User mode. USING R15 AS AN OPERANDY If R15 (the PC) is used as an operand in a data processing instruction the register is used directly. The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount the PC will be 12 bytes ahead. TEQ, TST, CMP AND CMN OPCODES NOTES TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in the CPSR. An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic. The TEQP form of the TEQ instruction used in earlier ARM processors must not be used: the PSR transfer operations should be used instead. The action of TEQP in the ARM920T is to move SPSR_ NOTE: S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively. 3-16 S3C2410X ARM INSTRUCTION SET ASSEMBLER SYNTAX * * * MOV,MVN (single operand instructions). where: EXAMPLES ADDEQ TEQS R2,R4,R5 R4,#3 ; ; ; ; ; ; ; ; ; ; If the Z flag is set make R2:=R4+R5 Test R4 for equality with 3. (The S is in fact redundant as the assembler inserts it automatically.) Logical right shift R7 by the number in the bottom byte of R2, subtract result from R5, and put the answer into R4. Return from subroutine. Return from exception and restore CPSR from SPSR_mode. SUB R4,R5,R7,LSR R2 MOV MOVS PC,R14 PC,R14 3-17 ARM INSTRUCTION SET S3C2410X PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11. These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the CPSR or SPSR_ * * * * * In user mode, the control bits of the CPSR are protected from change, so only the condition code flags of the CPSR can be changed. In other (privileged) modes the entire CPSR can be changed. Note that the software must never change the state of the T bit in the CPSR. If this happens, the processor will enter an unpredictable state. The SPSR register which is accessed depends on the mode at the time of execution. For example, only SPSR_fiq is accessible when the processor is in FIQ mode. You must not specify R15 as the source or destination register. Also, do not attempt to access an SPSR in User mode, since no such register exists. 3-18 S3C2410X ARM INSTRUCTION SET MRS (transfer PSR contents to a register) 31 Cond 28 27 00010 23 22 21 Ps 001111 16 15 Rd 12 11 000000000000 0 [15:12] Destination Register [22] Source PSR 0 = CPSR 1 = SPSR_ [31:28] Condition Field MSR (transfer register contents to PSR) 31 Cond 28 27 00010 23 22 21 Pd 101001111 12 11 00000000 43 Rm 0 [3:0] Source Register [22] Destination PSR 0 = CPSR 1 = SPSR_ [31:28] Condition Field MSR (transfer register contents or immediate value to PSR flag bits only) 31 Cond 28 27 26 25 24 23 22 21 00 I 10 Pd 101001111 12 11 Source operand 0 [22] Destination PSR 0 = CPSR 1 = SPSR_ [25] Immediate Operand 0 = Source operand is a register 1 = SPSR_ [11:0] Source Operand 11 00000000 43 Rm 0 [3:0] Source Register [11:4] Source operand is an immediate value 11 Rotate 87 Imm 0 [7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm [31:28] Condition Field Figure 3-11. PSR Transfer 3-19 ARM INSTRUCTION SET S3C2410X RESERVED BITS Only twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits. To ensure the maximum compatibility between ARM920T programs and future processors, the following rules should be observed: * * The reserved bits should be preserved when changing the value in a PSR. Programs should not rely on specific values from the reserved bits when checking the PSR status, since they may read as one or zero in future processors. A read-modify-write strategy should therefore be used when altering the control bits of any PSR register; this involves transferring the appropriate PSR register to a general register using the MRS instruction, changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction. EXAMPLES The following sequence performs a mode change: MRS BIC ORR MSR R0,CPSR R0,R0,#0x1F R0,R0,#new_mode CPSR,R0 ; ; ; ; Take a copy of the CPSR. Clear the mode bits. Select new mode Write back the modified CPSR. When the aim is simply to change the condition code flags in a PSR, a value can be written directly to the flag bits without disturbing the control bits. The following instruction sets the N,Z,C and V flags: MSR CPSR_flg,#0xF0000000 ; Set all the flags regardless of their previous state ; (does not affect any control bits). No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits. INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles, where S is defined as Sequential (S-cycle). 3-20 S3C2410X ARM INSTRUCTION SET ASSEMBLY SYNTAX * * * MRS - transfer PSR contents to a register MRS{cond} Rd, * MSR - transfer immediate value to PSR flag bits only MSR{cond} In privileged modes the instructions behave as follows: MSR MSR MSR MSR MSR MSR MRS CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0x50000000 SPSR_all,Rm SPSR_flg,Rm SPSR_flg,#0xC0000000 Rd,SPSR ; ; ; ; ; ; ; CPSR[31:0] <- Rm[31:0] CPSR[31:28] <- Rm[31:28] CPSR[31:28] <- 0x5 (set Z,V; clear N,C) SPSR_ 3-21 ARM INSTRUCTION SET S3C2410X MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication. 31 Cond 28 27 22 21 20 19 AS Rd 16 15 Rn 12 11 Rs 87 43 Rm 0 000000 1001 [15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Set Condition Code 0 = Do not after condition codes 1 = Set condition codes [21] Accumulate 0 = Multiply only 1 = Multiply and accumulate [31:28] Condition Field Figure 3-12. Multiply Instructions The multiply form of the instruction gives Rd:=Rm*Rs. Rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. The multiply-accumulate form gives Rd:=Rm*Rs+Rn, which can save an explicit ADD instruction in some circumstances. Both forms of the instruction work on operands which may be considered as signed (2's complement) or unsigned integers. The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical. As these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies. For example consider the multiplication of the operands: Operand A Operand B Result 0xFFFFFFF6 0x0000001 0xFFFFFF38 3-22 S3C2410X ARM INSTRUCTION SET If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38. If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38. Operand Restrictions The destination register Rd must not be the same as the operand register Rm. R15 must not be used as an operand or as the destination register. All other register combinations will give correct results, and Rd, Rn and Rs may use the same register when required. 3-23 ARM INSTRUCTION SET S3C2410X CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero). The C (Carry) flag is set to a meaningless value and the V (oVerflow) flag is unaffected. INSTRUCTION CYCLE TIMES MUL takes 1S + mI and MLA 1S + (m+1)I cycles to execute, where S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively. m which is The number of 8 bit multiplier array cycles is required to complete the multiply, controlled by the value of the multiplier operand specified by Rs. Its possible values are as follows 1 2 3 4 If bits [32:8] of the multiplier operand are all zero or all one. If bits [32:16] of the multiplier operand are all zero or all one. If bits [32:24] of the multiplier operand are all zero or all one. In all other cases. ASSEMBLER SYNTAX MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn {cond} {S} Two-character condition mnemonic. See Table 3-2.. Set condition codes if S present Rd, Rm, Rs and Rn Expressions evaluating to a register number other than R15. EXAMPLES MUL MLAEQS R1,R2,R3 R1,R2,R3,R4 ; R1:=R2*R3 ; Conditionally R1:=R2*R3+R4, Setting condition codes. 3-24 S3C2410X ARM INSTRUCTION SET MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. Signed and unsigned multiplication each with optional accumulate give rise to four variations. 31 Cond 28 27 23 22 21 20 19 UAS RdHi 16 15 RdLo 12 11 Rs 87 43 Rm 0 00001 1001 [11:8][3:0] Operand Registers [19:16][15:12] Source Destination Registers [20] Set Condition Code 0 = Do not alter condition codes 1 = Set condition codes [21] Accumulate 0 = Multiply only 1 = Multiply and accumulate [22] Unsigned 0 = Unsigned 1 = Signed [31:28] Condition Field Figure 3-13. Multiply Long Instructions The multiply forms (UMULL and SMULL) take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs. The lower 32 bits of the 64 bit result are written to RdLo, the upper 32 bits of the result are written to RdHi. The multiply-accumulate forms (UMLAL and SMLAL) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs + RdHi,RdLo. The lower 32 bits of the 64 bit number to add is read from RdLo. The upper 32 bits of the 64 bit number to add is read from RdHi. The lower 32 bits of the 64 bit result are written to RdLo. The upper 32 bits of the 64 bit result are written to RdHi. The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. The SMULL and SMLAL instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result. 3-25 ARM INSTRUCTION SET S3C2410X OPERAND RESTRICTIONS * * R15 must not be used as an operand or as a destination register. RdHi, RdLo, and Rm must all specify different registers. CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero). Both the C and V flags are set to meaningless values. INSTRUCTION CYCLE TIMES MULL takes 1S + (m+1)I and MLAL 1S + (m+2)I cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs. Its possible values are as follows: For Signed INSTRUCTIONS SMULL, SMLAL: * * * * If bits [31:8] of the multiplier operand are all zero or all one. If bits [31:16] of the multiplier operand are all zero or all one. If bits [31:24] of the multiplier operand are all zero or all one. In all other cases. For Unsigned Instructions UMULL, UMLAL: * * If bits [31:8] of the multiplier operand are all zero. If bits [31:16] of the multiplier operand are all zero. * If bits [31:24] of the multiplier operand are all zero. * In all other cases. S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively. 3-26 S3C2410X ARM INSTRUCTION SET ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic UMULL{cond}{S} RdLo,RdHi,Rm,Rs UMLAL{cond}{S} RdLo,RdHi,Rm,Rs SMULL{cond}{S} RdLo,RdHi,Rm,Rs SMLAL{cond}{S} RdLo,RdHi,Rm,Rs where: {cond} {S} RdLo, RdHi, Rm, Rs EXAMPLES UMULL UMLALS R1,R4,R2,R3 R1,R5,R2,R3 ; R4,R1:=R2*R3 ; R5,R1:=R2*R3+R5,R1 also setting condition codes Two-character condition mnemonic. See Table 3-2. Set condition codes if S present Expressions evaluating to a register number other than R15. Description Unsigned Multiply Long Unsigned Multiply & Accumulate Long Signed Multiply Long Signed Multiply & Accumulate Long Purpose 32 x 32 = 64 32 x 32 + 64 = 64 32 x 32 = 64 32 x 32 + 64 = 64 3-27 ARM INSTRUCTION SET S3C2410X SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required. 31 Cond 28 27 26 25 24 23 22 21 20 19 01 I PUBWL Rn 16 15 Rd 12 11 Offset 0 [15:12] Source/Destination Registers [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] Byte/Word Bit 0 = Transfer word quantity 1 = Transfer byte quantity [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset before transfer [25] Immediate Offset 0 = Offset is an immediate value [11:0] Offset 11 Immediate [11:0] Unsigned 12-bit immediate offset 11 Shift 43 Rm 0 0 [3:0] Offset register [11:4] Shift applied to Rm [31:28] Condition Field Figure 3-14. Single Data Transfer Instructions 3-28 S3C2410X ARM INSTRUCTION SET OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the base is used as the transfer address. The W bit gives optional auto increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base value may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The only use of the W bit in a post-indexed data transfer is in privileged mode code, where setting the W bit forces nonprivileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware. SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section. However, the register specified shift amounts are not available in this instruction class. See Figure 3-5. BYTES AND WORDS This instruction class may be used to transfer a byte (B=1) or a word (B=0) between an ARM920T register and memory. The action of LDR(B) and STR(B) instructions is influenced by the BIGEND control signal of ARM920T core. The two possible configurations are described below. Little-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. Please see Figure 2-2. A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) will normally use a word aligned address. However, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. This means that half-words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. Two shift operations are then required to clear or to sign extend the upper 16 bits. A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31. 3-29 ARM INSTRUCTION SET S3C2410X memory A A+3 B A+2 C A+1 D A 0 8 16 24 register A 24 B 16 C 8 D 0 LDR from word aligned address memory A A+3 B A+2 C A+1 D A 0 LDR from address offset by 2 8 D 0 16 C 8 24 B 16 register A 24 Figure 3-15. Little-Endian Offset Addressing Big-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. Please see Figure 2-1. A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data. A word load (LDR) should generate a word aligned address. An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. This means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. A shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8. A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31. 3-30 S3C2410X ARM INSTRUCTION SET USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. R15 must not be specified as the register offset (Rm). When R15 is the source register (Rd) of a register store (STR) instruction, the stored value will be address of the instruction plus 12. Restriction on the use of base register When configured for late aborts, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value. After an abort, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value. EXAMPLE: LDR R0,[R1],R1 Therefore a post-indexed LDR or STR where Rm is the same register as Rn should not be used. DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S + 1N + 1I and LDR PC take 2S + 2N +1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STR instructions take 2N incremental cycles to execute. 3-31 ARM INSTRUCTION SET S3C2410X ASSEMBLER SYNTAX can be: 1 An expression which generates an address: The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated. A pre-indexed addressing specification: [Rn] offset of zero [Rn,<#expression>]{!} offset of 2 3 3-32 S3C2410X ARM INSTRUCTION SET EXAMPLES STR STR LDR LDR LDREQB STR PLACE R1,[R2,R4]! R1,[R2],R4 R1,[R2,#16] R1,[R2,R3,LSL#2] R1,[R6,#5] R1,PLACE ; ; ; ; ; ; ; ; Store R1 at R2+R4 (both of which are registers) and write back address to R2. Store R1 at R2 and write back R2+R4 to R2. Load R1 from contents of R2+16, but don't write back. Load R1 from contents of R2+R3*4. Conditionally load byte at R6+5 into R1 bits 0 to 7, filling bits 8 to 31 with zeros. Generate PC relative offset to address PLACE. 3-33 ARM INSTRUCTION SET S3C2410X HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16. These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required. 31 Cond 28 27 000 25 24 23 22 21 20 19 PU0WL Rn 16 15 Rd 12 11 0000 876543 1SH1 Rm 0 [3:0] Offset Register [6][5] S H 0 0 1 1 0 = SWP instruction 1 = Unsigned halfword 1 = Signed byte 1 = Signed halfword [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 = Store to memory 1 = Load from memory [21] Write-back 0 = No write-back 1 = Write address into base [23] Up/Down 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing 0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer [31:28] Condition Field Figure 3-16. Halfword and Signed Data Transfer with Register Offset 3-34 S3C2410X ARM INSTRUCTION SET 31 Cond 28 27 000 25 24 23 22 21 20 19 PU1WL Rn 16 15 Rd 12 11 Offset 876543 1SH1 Offset 0 [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 1 1 0 = SWP instruction 1 = Unsigned halfword 1 = Signed byte 1 = Signed halfword [11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store 0 = Store to memory 1 = Load from memory [21] Write-back 0 = No write-back 1 = Write address into base [23] Up/Down 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing 0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer [31:28] Condition Field Figure 3-17. Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing OFFSETS AND AUTO-INDEXING The offset from the base may be either a 8-bit unsigned binary immediate value in the instruction, or a second register. The 8-bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word, such that bit 11 becomes the MSB and bit 0 becomes the LSB. The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (postindexed, P=0) the base register is used as the transfer address. The W bit gives optional auto-increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained if necessary by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The Write-back bit should not be set high (W=1) when post-indexed addressing is selected. 3-35 ARM INSTRUCTION SET S3C2410X HALFWORD LOAD AND STORES Setting S=0 and H=1 may be used to transfer unsigned Half-words between an ARM920T register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below. Signed byte and halfword loads The S bit controls the loading of sign-extended data. When S=1 the H bit selects between Bytes (H=0) and Halfwords (H=1). The L bit should not be set low (Store) when Signed (S=1) operations have been selected. The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7, the sign bit. The LDRSH instruction loads the selected Half-word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15, the sign bit. The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the following section. Endianness and byte/halfword selection Little-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary, on data bus inputs 15 through to 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-2. A halfword load (LDRSH or LDRH) expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a halfword boundary, (A[1]=1).The supplied address should always be on a halfword boundary. If bit 0 of the supplied address is HIGH then the ARM920T will load an unpredictable value. The selected halfword is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the halfword. A halfword store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate halfword subsystem to store the data. Note that the address must be halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable behaviour. 3-36 S3C2410X ARM INSTRUCTION SET Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-1. A halfword load (LDRSH or LDRH) expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary, (A[1]=1). The supplied address should always be on a halfword boundary. If bit 0 of the supplied address is HIGH then the ARM920T will load an unpredictable value. The selected halfword is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the halfword. A halfword store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate halfword subsystem to store the data. Note that the address must be halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable behaviour. USE OF R15 Write-back should not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. R15 should not be specified as the register offset (Rm). When R15 is the source register (Rd) of a Half-word store (STRH) instruction, the stored address will be address of the instruction plus 12. DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from the main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Normal LDR(H,SH,SB) instructions take 1S + 1N + 1I. LDR(H,SH,SB) PC take 2S + 2N + 1I incremental cycles. S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STRH instructions take 2N incremental cycles to execute. 3-37 ARM INSTRUCTION SET S3C2410X ASSEMBLER SYNTAX 2 3 4 the 3-38 S3C2410X ARM INSTRUCTION SET EXAMPLES LDRH ; ; ; R3,[R4,#14] ; R8,[R2],#-223 ; ; R11,[R0] ; ; ; R5, [PC,#(FRED-HERE-8)]; R1,[R2,-R3]! Load R1 from the contents of the halfword address contained in R2-R3 (both of which are registers) and write back address to R2 Store the halfword in R3 at R14+14 but don't write back. Load R8 with the sign extended contents of the byte address contained in R2 and write back R2-223 to R2. Conditionally load R11 with the sign extended contents of the halfword address contained in R0. Generate PC relative offset to address FRED. Store the halfword in R5 at address FRED STRH LDRSB LDRNESH HERE STRH FRED 3-39 ARM INSTRUCTION SET S3C2410X BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory. THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank (and non-user mode programs can also transfer to and from the user bank, see below). The register list is a 16 bit field in the instruction, with each bit corresponding to a register. A 1 in bit 0 of the register field will cause R0 to be transferred, a 0 will cause it not to be transferred; similarly bit 1 controls the transfer of R1, and so on. Any subset of the registers, or all the registers, may be specified. The only restriction is that the register list should not be empty. Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12. 31 Cond 28 27 100 25 24 23 22 21 20 19 PUSWL Rn 16 15 Register list 0 [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] PSR & Force User Bit 0 = Do not load PSR or user mode 1 = Load PSR or force user mode [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer [31:28] Condition Field Figure 3-18. Block Data Transfer Instructions 3-40 S3C2410X ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of the modified base is required (W=1). Figure 3.19-22 show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed. In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value. ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non-word aligned addresses do not affect the instruction. However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system. 0x100C 0x100C Rn 0x1000 R1 0x1000 0x0FF4 1 0x100C R5 R1 Rn R7 R5 R1 2 0x0FF4 0x100C 0x1000 0x1000 0x0FF4 3 4 0x0FF4 Figure 3-19. Post-Increment Addressing 3-41 ARM INSTRUCTION SET S3C2410X 0x100C R1 Rn 0x1000 0x100C 0x1000 0x0FF4 1 0x100C R5 R1 0x1000 Rn 2 R7 R5 R1 0x0FF4 0x100C 0x1000 0x0FF4 3 4 0x0FF4 Figure 3-20. Pre-Increment Addressing 0x100C 0x100C Rn 0x1000 R1 0x0FF4 1 0x100C 2 0x1000 0x0FF4 0x100C 0x1000 R5 R1 0x0FF4 3 Rn R7 R5 R1 0x1000 0x0FF4 4 Figure 3-21. Post-Decrement Addressing 3-42 S3C2410X ARM INSTRUCTION SET 0x100C 0x100C Rn 0x1000 0x1000 0x0FF4 1 0x100C R1 2 0x0FF4 0x100C 0x1000 R5 R1 3 R7 R5 R1 4 0x1000 0x0FF4 Rn 0x0FF4 Figure 3-22. Pre-Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode. LDM with R15 in Transfer List and S Bit Set (Mode Changes) If the instruction is a LDM then SPSR_ 3-43 ARM INSTRUCTION SET S3C2410X INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value. A LDM will always overwrite the updated base if the base is in the list. DATA ABORTS Some legal addresses may be unacceptable to a memory management system, and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH. This can happen on any transfer during a multiple register load or store, and must be recoverable if ARM920T is to be used in a virtual memory system. Abort during STM Instructions If the abort occurs during a store multiple instruction, ARM920T takes little action until the instruction completes, whereupon it enters the data abort trap. The memory manager is responsible for preventing erroneous writes to the memory. The only change to the internal state of the processor will be the modification of the base register if write-back was specified, and this must be reversed by software (and the cause of the abort resolved) before the instruction may be retried. Aborts during LDM Instructions When ARM920T detects a data abort during a load multiple instruction, it modifies the operation of the instruction to ensure that recovery is possible. * Overwriting of registers stops when the abort happens. The aborting load will not take place but earlier ones may have overwritten registers. The PC is always the last register to be written and so will always be preserved. The base register is restored, to its modified value if write-back was requested. This ensures recoverability in the case where the base register is also in the transfer list, and may have been overwritten before the abort occurred. * The data abort trap is taken when the load multiple has completed, and the system software must undo any base modification (and resolve the cause of the abort) before restarting the instruction. INSTRUCTION CYCLE TIMES Normal LDM instructions take nS + 1N + 1I and LDM PC takes (n+1)S + 2N + 1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STM instructions take (n-1)S + 2N incremental cycles to execute, where n is the number of words transferred. 3-44 S3C2410X ARM INSTRUCTION SET ASSEMBLER SYNTAX Addressing Mode Names There are different assembler mnemonics for each of the addressing modes, depending on whether the instruction is being used to support stacks or for other purposes. The equivalence between the names and the values of the bits in the instruction are shown in the following table 3-6. Table 3-6. Addressing Mode Names Name Pre-Increment Load Post-Increment Load Pre-Decrement Load Post-Decrement Load Pre-Increment Store Post-Increment Store Pre-Decrement Store Post-Decrement Store Stack LDMED LDMFD LDMEA LDMFA STMFA STMEA STMFD STMED Other LDMIB LDMIA LDMDB LDMDA STMIB STMIA STMDB STMDA L bit 1 1 1 1 0 0 0 0 P bit 1 0 1 0 1 0 1 0 U bit 1 1 0 0 1 1 0 0 FD, ED, FA, EA define pre/post indexing and the up/down bit by reference to the form of stack required. The F and E refer to a "full" or "empty" stack, i.e. whether a pre-index has to be done (full) before storing to the stack. The A and D refer to whether the stack is ascending or descending. If ascending, a STM will go up and LDM down, if descending, vice-versa. IA, IB, DA, DB allow control when LDM/STM are not being used for stacks and simply mean Increment After, Increment Before, Decrement After, Decrement Before. 3-45 ARM INSTRUCTION SET S3C2410X EXAMPLES LDMFD STMIA LDMFD LDMFD STMFD SP!,{R0,R1,R2} R0,{R0-R15} SP!,{R15} SP!,{R15}^ R13,{R0-R14}^ ; ; ; ; ; ; ; Unstack 3 registers. Save all registers. R15 (SP), CPSR unchanged. R15 (SP), CPSR <- SPSR_mode (allowed only in privileged modes). Save user mode regs on stack (allowed only in privileged modes). These instructions may be used to save state on subroutine entry, and restore it efficiently on return to the calling routine: STMED BL LDMED SP!,{R0-R3,R14} somewhere SP!,{R0-R3,R15} ; ; ; ; Save R0 to R3 to use as workspace and R14 for returning. This nested call will overwrite R14 Restore workspace and return. 3-46 S3C2410X ARM INSTRUCTION SET SINGLE DATA SWAP (SWP) 31 Cond 28 27 00010 23 22 21 20 19 B 00 Rn 16 15 Rd 12 11 0000 87 1001 43 Rm 0 [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field Figure 3-23. Swap Instruction The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-23. The data swap instruction is used to swap a byte or word quantity between a register and external memory. This instruction is implemented as a memory read followed by a memory write which are "locked" together (the processor cannot be interrupted until both operations have completed, and the memory manager is warned to treat them as inseparable). This class of instruction is particularly useful for implementing software semaphores. The swap address is determined by the contents of the base register (Rn). The processor first reads the contents of the swap address. Then it writes the contents of the source register (Rm) to the swap address, and stores the old memory contents in the destination register (Rd). The same register may be specified as both the source and destination. The LOCK output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together, and should be allowed to complete without interruption. This is important in multi-processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores; control of the memory must not be removed from a processor while it is performing a locked operation. BYTES AND WORDS This instruction class may be used to swap a byte (B=1) or a word (B=0) between an ARM920T register and memory. The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers. In particular, the description of Big and Little Endian configuration applies to the SWP instruction. 3-47 ARM INSTRUCTION SET S3C2410X USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction. DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Swap instructions take 1S + 2N +1I incremental cycles to execute, where S,N and I are defined as sequential (S-cycle), non-sequential, and internal (I-cycle), respectively. ASSEMBLER SYNTAX 3-48 S3C2410X ARM INSTRUCTION SET SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below. 31 Cond 28 27 1111 24 23 Comment Field (Ignored by Processor) 0 [31:28] Condition Field Figure 3-24. Software Interrupt Instruction The software interrupt instruction is used to enter Supervisor mode in a controlled manner. The instruction causes the software interrupt trap to be taken, which effects the mode change. The PC is then forced to a fixed value (0x08) and the CPSR is saved in SPSR_svc. If the SWI vector address is suitably protected (by external memory management hardware) from modification by the user, a fully protected operating system may be constructed. RETURN FROM THE SUPERVISOR The PC is saved in R14_svc upon entering the software interrupt trap, with the PC adjusted to point to the word after the SWI instruction. MOVS PC,R14_svc will return to the calling program and restore the CPSR. Note that the link mechanism is not re-entrant, so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR. COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor, and may be used to communicate information to the supervisor code. For instance, the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions. INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S + 1N incremental cycles to execute, where S and N are defined as sequential (S-cycle) and non-sequential (N-cycle). 3-49 ARM INSTRUCTION SET S3C2410X ASSEMBLER SYNTAX SWI{cond} *** Two character condition mnemonic, Table 3-2. Evaluated and placed in the comment field (which is ignored by ARM920T). ReadC WriteI+"k" 0 ; Get next character from read stream. ; Output a "k" to the write stream. ; Conditionally call supervisor with 0 in comment field. ; SWI entry point ; Addresses of supervisor routines ReadC WriteI Zero EQU 256 EQU 512 Supervisor STMFD LDR BIC MOV ADR LDR WriteIRtn *** EQU 0 R13,{R0-R2,R14} R0,[R14,#-4] R0,R0,#0xFF000000 R1,R0,LSR#8 R2,EntryTable R15,[R2,R1,LSL#2] ; ; ; ; ; ; ; ; ; SWI has routine required in bits 8-23 and data (if any) in bits 0-7. Assumes R13_svc points to a suitable stack Save work registers and return address. Get SWI instruction. Clear top 8 bits. Get routine offset. Get start address of entry table. Branch to appropriate routine. Enter with character in R0 bits 0-7. LDMFD R13,{R0-R2,R15}^ ; Restore workspace and return, ; restoring processor mode and flags. 3-50 S3C2410X ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS (CDP) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25. This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back to ARM920T, and it will not wait for the operation to complete. The coprocessor could contain a queue of such instructions awaiting execution, and their execution can overlap other activity, allowing the coprocessor and ARM920T to perform independent tasks in parallel. COPROCESSOR INSTRUCTIONS The S3C2410X, unlike some other ARM-based processors, does not have an external coprocessor interface. It does not have a on-chip coprocessor also. So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C2410X. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the S3C2410X, the coprocessor instructions are still described here in full for completeness. (Remember that any external coprocessor described in this section is a software emulation.) 31 Cond 28 27 1110 24 23 20 19 CRn 16 15 CRd 12 11 Cp# 87 Cp 543 0 CRm 0 CP Opc [3:0] Coprocessor operand register [7:5] Coprocessor information [11:8] Coprocessor number [15:12] Coprocessor destination register [19:16] Coprocessor operand register [23:20] Coprocessor operation code [31:28] Condition Field Figure 3-25. Coprocessor Data Operation Instruction Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM920T. The remaining bits are used by coprocessors. The above field names are used by convention, and particular coprocessors may redefine the use of all fields except CP# as appropriate. The CP# field is used to contain an identifying number (in the range 0 to 15) for each coprocessor, and a coprocessor will ignore any instruction which does not contain its number in the CP# field. The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field (and possibly in the CP field) on the contents of CRn and CRm, and place the result in CRd. 3-51 ARM INSTRUCTION SET S3C2410X INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle). Assembler syntax CDP{cond} p#, 3-52 S3C2410X ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors's registers directly to memory. ARM920T is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred. 31 Cond 28 27 110 25 24 23 22 21 20 19 PUNWL Rn 16 15 CRd 12 11 CP# 87 Offset 0 [7:0] Unsigned 8 Bit Immediate Offset [11:8] Coprocessor Number [15:12] Coprocessor Source/Destination Register [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] Transfer Length [23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset before transfer [31:28] Condition Field Figure 3-26. Coprocessor Data Transfer Instructions 3-53 ARM INSTRUCTION SET S3C2410X THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field. The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors, but by convention CRd is the register to be transferred (or the first register where more than one is to be transferred), and the N bit is used to choose one of two transfer length options. For instance N=0 could select the transfer of a single register, and N=1 could select the transfer of all the registers for context switching. ADDRESSING MODES ARM920T is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. Note, however, that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and specify byte offsets for single data transfers. The 8 bit unsigned immediate offset is shifted left 2 bits and either added to (U=1) or subtracted from (U=0) the base register (Rn); this calculation may be performed either before (P=1) or after (P=0) the base is used as the transfer address. The modified base value may be overwritten back into the base register (if W=1), or the old value of the base may be preserved (W=0). Note that post-indexed addressing modes require explicit setting of the W bit, unlike LDR and STR which always write-back when post-indexed. The value of the base register, modified by the offset in a pre-indexed instruction, is used as the address for the transfer of the first word. The second word (if more than one is transferred) will go to or come from an address one word (4 bytes) higher than the first transfer, and the address will be incremented by one word for each subsequent transfer. ADDRESS ALIGNMENT The base address should normally be a word aligned quantity. The bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system. Use of R15 If Rn is R15, the value used will be the address of the instruction plus 8 bytes. Base write-back to R15 must not be specified. DATA ABORTS If the address is legal but the memory manager generates an abort, the data trap will be taken. The write-back of the modified base will take place, but all other processor state will be preserved. The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved, and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried. Instruction cycle times Coprocessor data transfer instructions take (n-1)S + 2N + bI incremental cycles to execute, where: n b The number of words transferred. The number of cycles spent in the coprocessor busy-wait loop. S, N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. 3-54 S3C2410X ARM INSTRUCTION SET ASSEMBLER SYNTAX 1 2 3 NOTES Although the address offset is expressed in bytes, the instruction offset field is in words. The assembler will adjust the offset appropriately. 3-55 ARM INSTRUCTION SET S3C2410X COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM920T and a coprocessor. An example of a coprocessor to ARM920T register transfer (MRC) instruction would be a FIX of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to ARM920T register. A FLOAT of a 32 bit value in ARM920T register into a floating point value within the coprocessor illustrates the use of ARM920T register to coprocessor transfer (MCR). An important use of this instruction is to communicate control information directly from the coprocessor into the ARM920T CPSR flags. As an example, the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution. 31 Cond 28 27 1110 24 23 21 20 19 CRn 16 15 Rd 12 11 CP# 87 CP 543 1 CRm 0 CP Opc L [3:0] Coprocessor Operand Register [7:5] Coprocessor Information [11:8] Coprocessor Number [15:12] ARM Source/Destination Register [19:16] Coprocessor Source/Destination Register [20] Load/Store Bit 0 = Store to coprocessor 1 = Load from coprocessor [21] Coprocessor Operation Mode [31:28] Condition Field Figure 3-27. Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The CP# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon. The CP Opc, CRn, CP and CRm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. Other interpretations are allowed where the coprocessor functionality is incompatible with this one. The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform, CRn is the coprocessor register which is the source or destination of the transferred information, and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified. 3-56 S3C2410X ARM INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer. TRANSFERS FROM R15 A coprocessor register transfer from ARM920T with R15 as the source register will store the PC+12. INSTRUCTION CYCLE TIMES MRC instructions take 1S + (b+1)I +1C incremental cycles to execute, where S, I and C are defined as sequential (S-cycle), internal (I-cycle), and coprocessor register transfer (C-cycle), respectively. MCR instructions take 1S + bI +1C incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. ASSEMBLER SYNTAX EXAMPLES MRC p2,5,R3,c5,c6 ; ; ; ; ; ; ; ; Request coproc 2 to perform operation 5 on c5 and c6, and transfer the (single 32-bit word) result back to R3. Request coproc 6 to perform operation 0 on R4 and place the result in c6. Conditionally request coproc 3 to perform operation 9 (type 2) on c5 and c6, and transfer the result back to R3. MCR MRCEQ p6,0,R4,c5,c6 p3,9,R3,c5,c6,2 3-57 ARM INSTRUCTION SET S3C2410X UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 31 Cond 28 27 011 25 24 xxxxxxxxxxxxxxxxxxxx 543 1 xxxx 0 Figure 3-28. Undefined Instruction If the condition is true, the undefined instruction trap will be taken. Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving CPA and CPB HIGH. INSTRUCTION CYCLE TIMES This instruction takes 2S + 1I + 1N cycles, where S, N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle). ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction. If it is adopted in the future for some specified use, suitable mnemonics will be added to the assembler. Until such time, this instruction must not be used. 3-58 S3C2410X ARM INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code. USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP BEQ CMP BEQ This can be replaced by CMP CMPNE BEQ Absolute Value TEQ RSBMI Rn,#0 Rn,Rn,#0 ; Test sign ; and 2's complement if necessary. Rn,#p Rm,#q Label ; If condition not satisfied try other test. Rn,#p Label Rm,#q Label ; If Rn=p OR Rm=q THEN GOTO Label. Multiplication by 4, 5 or 6 (Run Time) MOV CMP ADDCS ADDHI Rc,Ra,LSL#2 Rb,#5 Rc,Rc,Ra Rc,Rc,Ra ; ; ; ; Multiply by 4, Test value, Complete multiply by 5, Complete multiply by 6. Combining Discrete and Range Tests TEQ CMPNE MOVLS Rc,#127 Rc,# " "-1 Rc,# "" ; ; ; ; Discrete test, Range test IF Rc<= "" OR Rc=ASCII(127) THEN Rc:= "." 3-59 ARM INSTRUCTION SET S3C2410X Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit, available from your supplier. A short general purpose divide routine follows. MOV CMP CMPCC MOVCC MOVCC BCC MOV CMP SUBCS ADDCS MOVS MOVNE BNE Rcnt,#1 Rb,#0x80000000 Rb,Ra Rb,Rb,ASL#1 Rcnt,Rcnt,ASL#1 Div1 Rc,#0 Ra,Rb Ra,Ra,Rb Rc,Rc,Rcnt Rcnt,Rcnt,LSR#1 Rb,Rb,LSR#1 Div2 ; Enter with numbers in Ra and Rb. ; Bit to control the division. ; Move Rb until greater than Ra. Div1 Div2 ; ; ; ; ; ; Test for possible subtraction. Subtract if ok, Put relevant bit into result Shift control bit Halve unless finished. Divide result in Rc, remainder in Ra. Overflow Detection in the ARM920T 1. Overflow in unsigned multiply with a 32-bit result UMULL TEQ BNE Rd,Rt,Rm,Rn Rt,#0 overflow ; 3 to 6 cycles ; +1 cycle and a register 2. Overflow in signed multiply with a 32-bit result SMULL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd ASR#31 overflow ; 3 to 6 cycles ; +1 cycle and a register 3. Overflow in unsigned multiply accumulate with a 32 bit result UMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,#0 overflow ; 4 to 7 cycles ; +1 cycle and a register 4. Overflow in signed multiply accumulate with a 32 bit result SMLAL TEQ BNE Rd,Rt,Rm,Rn Rt,Rd, ASR#31 overflow ; 4 to 7 cycles ; +1 cycle and a register 3-60 S3C2410X ARM INSTRUCTION SET 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL ADDS ADC BCS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers 6. Overflow in signed multiply accumulate with a 64 bit result SMULL ADDS ADC BVS Rl,Rh,Rm,Rn Rl,Rl,Ra1 Rh,Rh,Ra2 overflow ; ; ; ; 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers NOTES Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations. PSEUDO-RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-OR feedback rather like a cyclic redundancy check generator. Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33 bit register with taps at bits 33 and 20. The basic algorithm is newbit:=bit 33 eor bit 20, shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). The entire operation can be done in 5 S cycles: ; ; ; ; ; ; ; Enter with seed in Ra (32 bits), Rb (1 bit in Rb lsb), uses Rc. Top bit into carry 33 bit rotate right Carry into lsb of Rb (involved!) (similarly involved!) new seed in Ra, Rb as before TST MOVS ADC EOR EOR Rb,Rb,LSR#1 Rc,Ra,RRX Rb,Rb,Rb Rc,Rc,Ra,LSL#12 Ra,Rc,Rc,LSR#20 MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2^n (1,2,4,8,16,32..) MOV Ra, Rb, LSL #n Multiplication by 2^n+1 (3,5,9,17..) ADD Ra,Ra,Ra,LSL #n Multiplication by 2^n-1 (3,7,15..) RSB Ra,Ra,Ra,LSL #n 3-61 ARM INSTRUCTION SET S3C2410X Multiplication by 6 ADD MOV Ra,Ra,Ra,LSL #1 Ra,Ra,LSL#1 ; Multiply by 3 ; and then by 2 Multiply by 10 and add in extra number ADD ADD Ra,Ra,Ra,LSL#2 Ra,Rc,Ra,LSL#1 ; Multiply by 5 ; Multiply by 2 and add in next digit General recursive method for Rb := Ra*C, C a constant: 1. If C even, say C = 2^n*D, D odd: D=1: D<>1: MOV MOV Rb,Ra,LSL #n {Rb := Ra*D} Rb,Rb,LSL #n 2. If C MOD 4 = 1, say C = 2^n*D+1, D odd, n>1: D=1: D<>1: ADD ADD Rb,Ra,Ra,LSL #n {Rb := Ra*D} Rb,Ra,Rb,LSL #n 3. If C MOD 4 = 3, say C = 2^n*D-1, D odd, n>1: D=1: D<>1: RSB RSB Rb,Ra,Ra,LSL #n {Rb := Ra*D} Rb,Ra,Rb,LSL #n This is not quite optimal, but close. An example of its non-optimality is multiply by 45 which is done by: RSB RSB ADD rather than by: ADD ADD Rb,Ra,Ra,LSL#3 Rb,Rb,Rb,LSL#2 ; Multiply by 9 ; Multiply by 5*9 = 45 Rb,Ra,Ra,LSL#2 Rb,Ra,Rb,LSL#2 Rb,Ra,Rb,LSL# 2 ; Multiply by 3 ; Multiply by 4*3-1 = 11 ; Multiply by 4*11+1 = 45 3-62 S3C2410X ARM INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; ; ; ; ; ; ; ; ; Enter with address in Ra (32 bits) uses Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 Get word aligned address Get 64 bits containing answer Correction factor in bytes ...now in bits and test if aligned Produce bottom of result word (if not aligned) Get other shift amount Combine two halves to get result BIC LDMIA AND MOVS MOVNE RSBNE ORRNE Rb,Ra,#3 Rb,{Rd,Rc} Rb,Ra,#3 Rb,Rb,LSL#3 Rd,Rd,LSR Rb Rb,Rb,#32 Rd,Rd,Rc,LSL Rb 3-63 ARM INSTRUCTION SET S3C2410X NOTES 3-64 S3C2410X THUMB INSTRUCTION SET 4 THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core. As the Thumb instructions are compressed ARM instructions, the Thumb instructions have the 16-bit format instructions and have some restrictions. The restrictions by 16-bit format is fully notified for using the Thumb instructions. 4-1 THUMB INSTRUCTION SET S3C2410X FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure. 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 B 0 1 0 1 1 0 1 1 0 1 1 0 H 1 Op 0 0 1 L H L L L SP 0 L L 0 1 B S 0 1 Op 1 I 9 8 Offset5 7 6 5 4 Rs Rs 3 2 1 Rd Rd 0 Move Shifted register Add/subtract Move/compare/add/ subtract immediate Op Rd Rn/offset3 Offset8 Op Rs Rs/Hs Word8 Ro Ro Rb Rb Rb Rb Word8 Word8 0 R S SWord7 Rlist Rlist Softset8 1 Value8 Offset11 Offset Rd Rd Rd Rd Rd Rd/Hd ALU operations Hi register operations /branch exchange PC-relative load Load/store with register offset Load/store sign-extended byte/halfword Load/store with immediate offset Load/store halfword SP-relative load/store Load address Add offset to stack pointer Push/pop register Multiple load/store Conditional branch Software interrupt Unconditional branch Long branch with link Op Rd 0 1 H1 H2 Offset5 Offset5 Rd Rd 0 0 Rb Cond 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 4-1. THUMB Instruction Set Formats 4-2 S3C2410X THUMB INSTRUCTION SET OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 4-1. THUMB Instruction Set Opcodes Mnemonic ADC ADD AND ASR B Bxx BIC BL BX CMN CMP EOR LDMIA LDR LDRB LDRH LSL LDSB LDSH LSR MOV MUL MVN Instruction Add with Carry Add AND Arithmetic Shift Right Unconditional branch Conditional branch Bit Clear Branch and Link Branch and Exchange Compare Negative Compare EOR Load multiple Load word Load byte Load halfword Logical Shift Left Load sign-extended byte Load sign-extended halfword Logical Shift Right Move register Multiply Move Negative register Lo-Register Operand Y Y Y Y Y Y Y - Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Hi-Register Operand - - - - - - - - Y - Y - - - - - - - - - Y - - Condition Codes Set Y Y (1) Y Y - - Y - - Y Y Y - - - - Y - - Y Y (2) Y Y 4-3 THUMB INSTRUCTION SET S3C2410X Table 4-1. THUMB Instruction Set Opcodes (Continued) Mnemonic NEG ORR POP PUSH ROR SBC STMIA STR STRB STRH SWI SUB TST Negate OR Pop register Push register Rotate Right Subtract with Carry Store Multiple Store word Store byte Store halfword Software Interrupt Subtract Test bits Instruction Lo-Register Operand Y Y Y Y Y Y Y Y Y Y - Y Y Hi-Register Operand - - - - - - - - - - - - - Condition Codes Set Y Y - - Y Y - - - - - Y Y NOTES: 1. The condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. The condition codes are unaffected by the format 5 version of this instruction. 4-4 S3C2410X THUMB INSTRUCTION SET FORMAT 1: MOVE SHIFTED REGISTER 15 0 14 0 13 0 12 Op 11 10 Offset5 6 5 Rs 3 2 Rd 0 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Figure 4-2. Format 1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 4-2. NOTE All instructions in this group set the CPSR condition codes. Table 4-2. Summary of Format 1 Instructions OP 00 01 THUMB Assembler LSL Rd, Rs, #Offset5 LSR Rd, Rs, #Offset5 ARM Equipment Action MOVS Rd, Rs, LSL #Offset5 Shift Rs left by a 5-bit immediate value and store the result in Rd. MOVS Rd, Rs, LSR #Offset5 Perform logical shift right on Rs by a 5-bit immediate value and store the result in Rd. MOVS Rd, Rs, ASR #Offset5 Perform arithmetic shift right on Rs by a 5-bit immediate value and store the result in Rd. 10 ASR Rd, Rs, #Offset5 4-5 THUMB INSTRUCTION SET S3C2410X INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-2. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LSR R2, R5, #27 ; Logical shift right the contents ; of R5 by 27 and store the result in R2. ; Set condition codes on the result. 4-6 S3C2410X THUMB INSTRUCTION SET FORMAT 2: ADD/SUBTRACT 15 0 14 0 13 0 12 1 11 1 10 1 9 Op 8 Rn/Offset3 6 5 Rs 3 2 Rd 0 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Figure 4-3. Format 2 OPERATION These instructions allow the contents of a Lo register or a 3-bit immediate value to be added to or subtracted from a Lo register. The THUMB assembler syntax is shown in Table 4-3. NOTE All instructions in this group set the CPSR condition codes. Table 4-3. Summary of Format 2 Instructions OP 0 0 1 1 I 0 1 0 1 THUMB Assembler ADD Rd, Rs, Rn ADD Rd, Rs, #Offset3 SUB Rd, Rs, Rn SUB Rd, Rs, #Offset3 ARM Equipment ADDS Rd, Rs, Rn Action Add contents of Rn to contents of Rs. Place result in Rd. ADDS Rd, Rs, #Offset3 Add 3-bit immediate value to contents of Rs. Place result in Rd. SUBS Rd, Rs, Rn Subtract contents of Rn from contents of Rs. Place result in Rd. SUBS Rd, Rs, #Offset3 Subtract 3-bit immediate value from contents of Rs. Place result in Rd. 4-7 THUMB INSTRUCTION SET S3C2410X INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-3. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD SUB R0, R3, R4 R6, R2, #6 ; R0 := R3 + R4 and set condition codes on the result. ; R6 := R2 - 6 and set condition codes. 4-8 S3C2410X THUMB INSTRUCTION SET FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE 15 0 14 0 13 0 12 Op 11 10 Rd 8 7 Offset8 0 [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Figure 4-4. Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 4-4. NOTE All instructions in this group set the CPSR condition codes. Table 4-4. Summary of Format 3 Instructions OP 00 01 10 11 THUMB Assembler MOV Rd, #Offset8 CMP Rd, #Offset8 ADD Rd, #Offset8 SUB Rd, #Offset8 ARM Equipment MOVS Rd, #Offset8 CMP Rd, #Offset8 ADDS Rd, Rd, #Offset8 SUBS Rd, Rd, #Offset8 Action Move 8-bit immediate value into Rd. Compare contents of Rd with 8-bit immediate value. Add 8-bit immediate value to contents of Rd and place the result in Rd. Subtract 8-bit immediate value from contents of Rd and place the result in Rd. 4-9 THUMB INSTRUCTION SET S3C2410X INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-4. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES MOV CMP ADD SUB R0, #128 R2, #62 R1, #255 R6, #145 ; ; ; ; R0 := 128 and set condition codes Set condition codes on R2 - 62 R1 := R1 + 255 and set condition codes R6 := R6 - 145 and set condition codes 4-10 S3C2410X THUMB INSTRUCTION SET FORMAT 4: ALU OPERATIONS 15 0 14 0 13 0 12 0 11 0 10 0 9 Op 6 5 Rs 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode Figure 4-5. Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition codes. Table 4-5. Summary of Format 4 Instructions OP 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 THUMB Assembler AND Rd, Rs EOR Rd, Rs LSL Rd, Rs LSR Rd, Rs ASR Rd, Rs ADC Rd, Rs SBC Rd, Rs ROR Rd, Rs TST Rd, Rs NEG Rd, Rs CMP Rd, Rs CMN Rd, Rs ORR Rd, Rs MUL Rd, Rs BIC Rd, Rs MVN Rd, Rs ARM Equipment ANDS Rd, Rd, Rs EORS Rd, Rd, Rs MOVS Rd, Rd, LSL Rs MOVS Rd, Rd, LSR Rs MOVS Rd, Rd, ASR Rs ADCS Rd, Rd, Rs SBCS Rd, Rd, Rs MOVS Rd, Rd, ROR Rs TST Rd, Rs RSBS Rd, Rs, #0 CMP Rd, Rs CMN Rd, Rs ORRS Rd, Rd, Rs MULS Rd, Rs, Rd BICS Rd, Rd, Rs MVNS Rd, Rs Action Rd:= Rd AND Rs Rd:= Rd EOR Rs Rd := Rd << Rs Rd := Rd >> Rs Rd := Rd ASR Rs Rd := Rd + Rs + C-bit Rd := Rd - Rs - NOT C-bit Rd := Rd ROR Rs Set condition codes on Rd AND Rs Rd = - Rs Set condition codes on Rd - Rs Set condition codes on Rd + Rs Rd := Rd OR Rs Rd := Rs * Rd Rd := Rd AND NOT Rs Rd := NOT Rs 4-11 THUMB INSTRUCTION SET S3C2410X INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-5. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES EOR ROR NEG CMP MUL R3, R4 R1, R0 R5, R3 R2, R6 R0, R7 ; ; ; ; ; ; ; R3 := R3 EOR R4 and set condition codes Rotate Right R1 by the value in R0, store the result in R1 and set condition codes Subtract the contents of R3 from zero, Store the result in R5. Set condition codes ie R5 = - R3 Set the condition codes on the result of R2 - R6 R0 := R7 * R0 and set condition codes 4-12 S3C2410X THUMB INSTRUCTION SET FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE 15 0 14 0 13 0 12 0 11 0 10 0 9 Op 8 7 H1 6 H2 5 Rs/Hs 3 2 Rd/Hd 0 [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode Figure 4-6. Format 5 OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers, or a pair of Hi registers. The fourth, BX, allows a Branch to be performed which may also be used to switch processor state. The THUMB assembler syntax is shown in Table 4-6. NOTES In this group only CMP (Op = 01) sets the CPSR condition codes. The action of H1= 0, H2 = 0 for Op = 00 (ADD), Op =01 (CMP) and Op = 10 (MOV) is undefined, and should not be used. Table 4-6. Summary of Format 5 Instructions Op 00 00 00 01 H1 0 1 1 0 H2 1 0 1 1 THUMB assembler ADD Rd, Hs ADD Hd, Rs ADD Hd, Hs CMP Rd, Hs ARM equivalent ADD Rd, Rd, Hs ADD Hd, Hd, Rs ADD Hd, Hd, Hs CMP Rd, Hs Action Add a register in the range 8-15 to a register in the range 0-7. Add a register in the range 0-7 to a register in the range 8-15. Add two registers in the range 8-15 Compare a register in the range 0-7 with a register in the range 8-15. Set the condition code flags on the result. Compare a register in the range 8-15 with a register in the range 0-7. Set the condition code flags on the result. 01 1 0 CMP Hd, Rs CMP Hd, Rs 4-13 THUMB INSTRUCTION SET S3C2410X Table 4-6. Summary of Format 5 Instructions (Continued) Op 01 H1 1 H2 1 THUMB assembler CMP Hd, Hs ARM equivalent CMP Hd, Hs Action Compare two registers in the range 8-15. Set the condition code flags on the result. Move a value from a register in the range 8-15 to a register in the range 07. Move a value from a register in the range 0-7 to a register in the range 8-15. Move a value between two registers in the range 8-15. Perform branch (plus optional state change) to address in a register in the range 0-7. Perform branch (plus optional state change) to address in a register in the range 8-15. 10 0 1 MOV Rd, Hs MOV Rd, Hs 10 1 0 MOV Hd, Rs MOV Hd, Rs 10 11 1 0 1 0 MOV Hd, Hs BX Rs MOV Hd, Hs BX Rs 11 0 1 BX Hs BX Hs INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-6. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. THE BX INSTRUCTION BX performs a Branch to a routine whose start address is specified in a Lo or Hi register. Bit 0 of the address determines the processor state on entry to the routine: Bit 0 = 0 Bit 0 = 1 Causes the processor to enter ARM state. Causes the processor to enter THUMB state. NOTE The action of H1 = 1 for this instruction is undefined, and should not be used. 4-14 S3C2410X THUMB INSTRUCTION SET EXAMPLES Hi-Register Operations ADD CMP MOV PC, R5 R4, R12 R15, R14 ; ; ; ; ; PC := PC + R5 but don't set the condition codes. Set the condition codes on the result of R4 - R12. Move R14 (LR) into R15 (PC) but don't set the condition codes, eg. return from subroutine. Branch and Exchange ADR MOV BX R1,outofTHUMB R11,R1 R11 ; Switch from THUMB to ARM state. ; Load address of outofTHUMB into R1. ; Transfer the contents of R11 into the PC. ; Bit 0 of R11 determines whether ; ARM or THUMB state is entered, ie. ARM state here. * * ALIGN CODE32 outofTHUMB ; Now processing ARM instructions... USING R15 AS AN OPERAND If R15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. Executing a BX PC in THUMB state from a non-word aligned address will result in unpredictable execution. 4-15 THUMB INSTRUCTION SET S3C2410X FORMAT 6: PC-RELATIVE LOAD 15 0 14 0 13 0 12 0 11 0 10 Rd 8 7 Word 8 0 [7:0] Immediate Value [10:8] Destination Register Figure 4-7. Format 6 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below. Table 4-7. Summary of PC-Relative Load Instruction THUMB assembler LDR Rd, [PC, #Imm] ARM equivalent LDR Rd, [R15, #Imm] Action Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the PC. Load the word from the resulting address into Rd. NOTE: The value specified by #Imm is a full 10-bit address, but must always be word-aligned (ie with bits 1:0 set to 0), since the assembler places #Imm >> 2 in field Word 8. The value of the PC will be 4 bytes greater than the address of this instruction, but bit 1 of the PC is forced to 0 to ensure it is word aligned. 4-16 S3C2410X THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R3,[PC,#844] ; ; ; ; ; Load into R3 the word found at the address formed by adding 844 to PC. bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 211 as the Word8 value. 4-17 THUMB INSTRUCTION SET S3C2410X FORMAT 7: LOAD/STORE WITH REGISTER OFFSET 15 0 14 1 13 0 12 1 11 L 10 B 9 0 8 Ro 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 4-8. Format 7 4-18 S3C2410X THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are preindexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 4-8. Table 4-8. Summary of Format 7 Instructions L 0 B 0 THUMB assembler STR Rd, [Rb, Ro] ARM equivalent STR Rd, [Rb, Ro] Action Pre-indexed word store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the contents of Rd at the address. Pre-indexed byte store: Calculate the target address by adding together the value in Rb and the value in Ro. Store the byte value in Rd at the resulting address. Pre-indexed word load: Calculate the source address by adding together the value in Rb and the value in Ro. Load the contents of the address into Rd. Pre-indexed byte load: Calculate the source address by adding together the value in Rb and the value in Ro. Load the byte value at the resulting address. 0 1 STRB Rd, [Rb, Ro] STRB Rd, [Rb, Ro] 1 0 LDR Rd, [Rb, Ro] LDR Rd, [Rb, Ro] 1 1 LDRB Rd, [Rb, Ro] LDRB Rd, [Rb, Ro] INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-8. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR LDRB R3, [R2,R6] R2, [R0,R7] ; ; ; ; Store word in R3 at the address formed by adding R6 to R2. Load into R2 the byte found at the address formed by adding R7 to R0. 4-19 THUMB INSTRUCTION SET S3C2410X FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD 15 0 14 1 13 0 12 1 11 H 10 S 9 1 8 Ro 6 5 Rb 3 2 Rd 0 [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag Figure 4-9. Format 8 OPERATION These instructions load optionally sign-extended bytes or halfwords, and store halfwords. The THUMB assembler syntax is shown below. Table 4-9. Summary of format 8 instructions L 0 B 0 THUMB assembler STRH Rd, [Rb, Ro] ARM equivalent STRH Rd, [Rb, Ro] Store halfword: Add Ro to base address in Rb. Store bits 0-15 of Rd at the resulting address. 0 1 LDRH Rd, [Rb, Ro] LDRH Rd, [Rb, Ro] Load halfword: Add Ro to base address in Rb. Load bits 0-15 of Rd from the resulting address, and set bits 16-31 of Rd to 0. 1 0 LDSB Rd, [Rb, Ro] LDRSB Rd, [Rb, Ro] Load sign-extended byte: Add Ro to base address in Rb. Load bits 0-7 of Rd from the resulting address, and set bits 8-31 of Rd to bit 7. 1 1 LDSH Rd, [Rb, Ro] LDRSH Rd, [Rb, Ro] Load sign-extended halfword: Add Ro to base address in Rb. Load bits 0-15 of Rd from the resulting address, and set bits 16-31 of Rd to bit 15. Action 4-20 S3C2410X THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH LDSB LDSH R4, [R3, R0] R2, [R7, R1] R3, [R4, R2] ; ; ; ; ; ; Store the lower 16 bits of R4 at the address formed by adding R0 to R3. Load into R2 the sign extended byte found at the address formed by adding R1 to R7. Load into R3 the sign extended halfword found at the address formed by adding R2 to R4. 4-21 THUMB INSTRUCTION SET S3C2410X FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET 15 0 14 1 13 1 12 B 11 L 10 Offset5 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity Figure 4-10. Format 9 4-22 S3C2410X THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. The THUMB assembler syntax is shown in Table 4-10. Table 4-10. Summary of Format 9 Instructions L 0 B 0 THUMB assembler STR Rd, [Rb, #Imm] ARM equivalent STR Rd, [Rb, #Imm] Action Calculate the target address by adding together the value in Rb and Imm. Store the contents of Rd at the address. Calculate the source address by adding together the value in Rb and Imm. Load Rd from the address. Calculate the target address by adding together the value in Rb and Imm. Store the byte value in Rd at the address. Calculate source address by adding together the value in Rb and Imm. Load the byte value at the address into Rd. 1 0 LDR Rd, [Rb, #Imm] LDR Rd, [Rb, #Imm] 0 1 STRB Rd, [Rb, #Imm] STRB Rd, [Rb, #Imm] 1 1 LDRB Rd, [Rb, #Imm] LDRB Rd, [Rb, #Imm] NOTE: For word accesses (B = 0), the value specified by #Imm is a full 7-bit address, but must be word-aligned (ie with bits 1:0 set to 0), since the assembler places #Imm >> 2 in the Offset5 field. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-10. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R2, [R5,#116] ; ; ; ; ; ; ; ; Load into R2 the word found at the address formed by adding 116 to R5. Note that the THUMB opcode will contain 29 as the Offset5 value. Store the lower 8 bits of R1 at the address formed by adding 13 to R0. Note that the THUMB opcode will contain 13 as the Offset5 value. STRB R1, [R0,#13] 4-23 THUMB INSTRUCTION SET S3C2410X FORMAT 10: LOAD/STORE HALFWORD 15 0 14 1 13 0 12 0 11 L 10 Offset5 6 5 Rb 3 2 Rd 0 [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 4-11. Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory. Addresses are pre-indexed, using a 6-bit immediate value. The THUMB assembler syntax is shown in Table 4-11. Table 4-11. Halfword Data Transfer Instructions L 0 1 THUMB assembler STRH Rd, [Rb, #Imm] LDRH Rd, [Rb, #Imm] ARM equivalent STRH Rd, [Rb, #Imm] LDRH Rd, [Rb, #Imm] Action Add #Imm to base address in Rb and store bits 0 - 15 of Rd at the resulting address. Add #Imm to base address in Rb. Load bits 0-15 from the resulting address into Rd and set bits 16-31 to zero. NOTE: #Imm is a full 6-bit address but must be halfword-aligned (ie with bit 0 set to 0) since the assembler places #Imm >> 1 in the Offset5 field. 4-24 S3C2410X THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STRH R6, [R1, #56] ; ; ; ; ; ; Store the lower 16 bits of R4 at the address formed by adding 56 R1. Note that the THUMB opcode will contain 28 as the Offset5 value. Load into R4 the halfword found at the address formed by adding 4 to R7. Note that the THUMB opcode will contain 2 as the Offset5 value. LDRH R4, [R7, #4] 4-25 THUMB INSTRUCTION SET S3C2410X FORMAT 11: SP-RELATIVE LOAD/STORE 15 1 14 0 13 0 12 1 11 L 10 Rd 8 7 Word 8 0 [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-12. Format 11 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the following table. Table 4-12. SP-Relative Load/Store Instructions L 0 THUMB assembler STR Rd, [SP, #Imm] ARM equivalent STR Rd, [R13 #Imm] Action Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Store the contents of Rd at the resulting address. Add unsigned offset (255 words, 1020 bytes) in Imm to the current value of the SP (R7). Load the word from the resulting address into Rd. 1 LDR Rd, [SP, #Imm] LDR Rd, [R13 #Imm] NOTE: The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0), since the assembler places #Imm >> 2 in the Word8 field. 4-26 S3C2410X THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STR R4, [SP,#492] ; ; ; ; Store the contents of R4 at the address formed by adding 492 to SP (R13). Note that the THUMB opcode will contain 123 as the Word8 value. 4-27 THUMB INSTRUCTION SET S3C2410X FORMAT 12: LOAD ADDRESS 15 1 14 0 13 1 12 0 11 SP 10 Rd 8 7 Word 8 0 [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP Figure 4-13. Format 12 OPERATION These instructions calculate an address by adding an 10-bit constant to either the PC or the SP, and load the resulting address into a register. The THUMB assembler syntax is shown in the following table. Table 4-13. Load Address L 0 THUMB assembler ADD Rd, PC, #Imm ARM equivalent ADD Rd, R15, #Imm Action Add #Imm to the current value of the program counter (PC) and load the result into Rd. Add #Imm to the current value of the stack pointer (SP) and load the result into Rd. 1 ADD Rd, SP, #Imm ADD Rd, R13, #Imm NOTE: The value specified by #Imm is a full 10-bit value, but this must be word-aligned (ie with bits 1:0 set to 0) since the assembler places #Imm >> 2 in field Word 8. Where the PC is used as the source register (SP = 0), bit 1 of the PC is always read as 0. The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0. The CPSR condition codes are unaffected by these instructions. 4-28 S3C2410X THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-13. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD R2, PC, #572 ; ; ; ; ; ; ; ; R2 := PC + 572, but don't set the condition codes. bit[1] of PC is forced to zero. Note that the THUMB opcode will contain 143 as the Word8 value. R6 := SP (R13) + 212, but don't set the condition codes. Note that the THUMB opcode will contain 53 as the Word 8 value. ADD R6, SP, #212 4-29 THUMB INSTRUCTION SET S3C2410X FORMAT 13: ADD OFFSET TO STACK POINTER 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 S 6 SWord 7 0 [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative Figure 4-14. Format 13 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the THUMB assembler syntax. Table 4-14. The ADD SP Instruction L 0 1 THUMB assembler ADD SP, #Imm ADD SP, # -Imm ARM equivalent ADD R13, R13, #Imm SUB R13, R13, #Imm Action Add #Imm to the stack pointer (SP). Add #-Imm to the stack pointer (SP). NOTE: The offset specified by #Imm can be up to -/+ 508, but must be word-aligned (ie with bits 1:0 set to 0) since the assembler converts #Imm to an 8-bit sign + magnitude number before placing it in field SWord7. The condition codes are not set by this instruction. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-14. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES ADD SP, #268 ; ; ; ; ; ; SP (R13) := SP + 268, but don't set the condition codes. Note that the THUMB opcode will contain 67 as the Word7 value and S=0. SP (R13) := SP - 104, but don't set the condition codes. Note that the THUMB opcode will contain 26 as the Word7 value and S=1. ADD SP, #-104 4-30 S3C2410X THUMB INSTRUCTION SET FORMAT 14: PUSH/POP REGISTERS 15 1 14 0 13 1 12 1 11 L 10 1 9 0 8 R 7 Rlist 0 [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-15. Format 14 OPERATION The instructions in this group allow registers 0-7 and optionally LR to be pushed onto the stack, and registers 0-7 and optionally PC to be popped off the stack. The THUMB assembler syntax is shown in Table 4-15. NOTE The stack is always assumed to be Full Descending. Table 4-15. PUSH and POP Instructions L 0 0 B 0 1 THUMB assembler PUSH { Rlist } PUSH { Rlist, LR } ARM equivalent STMDB R13!, { Rlist } STMDB R13!, { Rlist, R14 } LDMIA R13!, { Rlist } Action Push the registers specified by Rlist onto the stack. Update the stack pointer. Push the Link Register and the registers specified by Rlist (if any) onto the stack. Update the stack pointer. Pop values off the stack into the registers specified by Rlist. Update the stack pointer. 1 0 POP { Rlist } 1 1 POP { Rlist, PC } LDMIA R13!, {Rlist, R15} Pop values off the stack and load into the registers specified by Rlist. Pop the PC off the stack. Update the stack pointer. 4-31 THUMB INSTRUCTION SET S3C2410X INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES PUSH {R0-R4,LR} ; ; ; ; ; ; ; Store R0,R1,R2,R3,R4 and R14 (LR) at the stack pointed to by R13 (SP) and update R13. Useful at start of a sub-routine to save workspace and return address. Load R2,R6 and R15 (PC) from the stack pointed to by R13 (SP) and update R13. Useful to restore workspace and return from sub-routine. POP {R2,R6,PC} 4-32 S3C2410X THUMB INSTRUCTION SET FORMAT 15: MULTIPLE LOAD/STORE 15 1 14 1 13 0 12 0 11 L 10 Rb 8 7 Rlist 0 [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 4-16. Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table. Table 4-16. The Multiple Load/Store Instructions L 0 THUMB assembler STMIA Rb!, { Rlist } ARM equivalent STMIA Rb!, { Rlist } Action Store the registers specified by Rlist, starting at the base address in Rb. Write back the new base address. Load the registers specified by Rlist, starting at the base address in Rb. Write back the new base address. 1 LDMIA Rb!, { Rlist } LDMIA Rb!, { Rlist } INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-16. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES STMIA R0!, {R3-R7} ; ; ; ; Store the contents of registers R3-R7 starting at the address specified in R0, incrementing the addresses for each word. Write back the updated value of R0. 4-33 THUMB INSTRUCTION SET S3C2410X FORMAT 16: CONDITIONAL BRANCH 15 1 14 1 13 0 12 1 11 Cond 8 7 SOffset 8 0 [7:0] 8-bit Signed Immediate [11:8] Condition Figure 4-17. Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. The THUMB assembler syntax is shown in the following table. Table 4-17. The Conditional Branch Instructions L 0000 0001 0010 0011 0100 0101 0110 0111 1000 THUMB assembler BEQ label BNE label BCS label BCC label BMI label BPL label BVS label BVC label BHI label ARM equivalent BEQ label BNE label BCS label BCC label BMI label BPL label BVS label BVC label BHI label Action Branch if Z set (equal) Branch if Z clear (not equal) Branch if C set (unsigned higher or same) Branch if C clear (unsigned lower) Branch if N set (negative) Branch if N clear (positive or zero) Branch if V set (overflow) Branch if V clear (no overflow) Branch if C set and Z clear (unsigned higher) 4-34 S3C2410X THUMB INSTRUCTION SET Table 4-17. The Conditional Branch Instructions (Continued) L 1001 1010 1011 1100 1101 THUMB assembler BLS label BGE label BLT label BGT label BLE label ARM equivalent BLS label BGE label BLT label BGT label BLE label Action Branch if C clear or Z set (unsigned lower or same) Branch if N set and V set, or N clear and V clear (greater or equal) Branch if N set and V clear, or N clear and V set (less than) Branch if Z clear, and either N set and V set or N clear and V clear (greater than) Branch if Z set, or N set and V clear, or N clear and V set (less than or equal) NOTES: 1. While label specifies a full 9-bit two's complement address, this must always be halfword-aligned (ie with bit 0 set to 0) since the assembler actually places label >> 1 in field SOffset8. 2. Cond = 1110 is undefined, and should not be used. Cond = 1111 creates the SWI instruction: see . INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-1. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES CMP R0, #45 BGT over * * * ; Branch to over-if R0 > 45. ; Note that the THUMB opcode will contain ; the number of halfwords to offset. ; Must be halfword aligned. over 4-35 THUMB INSTRUCTION SET S3C2410X FORMAT 17: SOFTWARE INTERRUPT 15 1 14 1 13 0 12 1 11 1 10 1 9 1 8 1 7 Value 8 0 [7:0] Comment Field Figure 4-18. Format 17 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode. The THUMB assembler syntax for this instruction is shown below. Table 4-18. The SWI Instruction THUMB assembler SWI Value 8 ARM equivalent SWI Value 8 Action Perform Software Interrupt: Move the address of the next instruction into LR, move CPSR to SPSR, load the SWI vector address (0x8) into the PC. Switch to ARM state and enter SVC mode. NOTE: Value8 is used solely by the SWI handler; it is ignored by the processor. INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-18. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES SWI 18 ; Take the software interrupt exception. ; Enter Supervisor mode with 18 as the ; requested SWI number. 4-36 S3C2410X THUMB INSTRUCTION SET FORMAT 18: UNCONDITIONAL BRANCH 15 1 14 1 13 1 12 0 11 0 10 Offset11 0 [10:0] Immediate Value Figure 4-19. Format 18 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction. Table 4-19. Summary of Branch Instruction THUMB assembler B label ARM equivalent BAL label (halfword offset) Action Branch PC relative +/- Offset11 << 1, where label is PC +/- 2048 bytes. NOTE: The address specified by label is a full 12-bit two's complement address, but must always be halfword aligned (ie bit 0 set to 0), since the assembler places label >> 1 in the Offset11 field. EXAMPLES here B here B jimmy * * * ; ; ; ; Branch onto itself. Assembles to 0xE7FE. (Note effect of PC offset). Branch to 'jimmy'. Note that the THUMB opcode will contain the number of jimmy * ; halfwords to offset. ; Must be halfword aligned. 4-37 THUMB INSTRUCTION SET S3C2410X FORMAT 19: LONG BRANCH WITH LINK 15 1 14 1 13 1 12 1 11 H 10 Offset 0 [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low Figure 4-20. Format 19 OPERATION This format specifies a long branch with link. The assembler splits the 23-bit two's complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two THUMB instructions. Instruction 1 (H = 0) In the first instruction the Offset field contains the upper 11 bits of the target address. This is shifted left by 12 bits and added to the current PC address. The resulting address is placed in LR. Instruction 2 (H =1) In the second instruction the Offset field contains an 11-bit representation lower half of the target address. This is shifted left by 1 bit and added to LR. LR, which now contains the full 23-bit address, is placed in PC, the address of the instruction following the BL is placed in LR and bit 0 of LR is set. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction 4-38 S3C2410X THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 4-20. The BL Instruction L 0 1 THUMB assembler BL label none ARM equivalent Action LR := PC + OffsetHigh << 12 temp := next instruction address PC := LR + OffsetLow << 1 LR := temp | 1 EXAMPLES BL faraway next * * faraway * * ; ; ; ; ; ; ; Unconditionally Branch to 'faraway' and place following instruction address, ie "next", in R14,the Link register and set bit 0 of LR high. Note that the THUMB opcodes will contain the number of halfwords to offset. Must be Half-word aligned. 4-39 THUMB INSTRUCTION SET S3C2410X INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1, 2 or 3 Thumb instructions alongside the ARM equivalents. For other constants it is generally better to use the built-in MUL instruction rather than using a sequence of 4 or more instructions. Thumb ARM 1. Multiplication by 2^n (1,2,4,8,...) LSL Ra, Rb, LSL #n ; MOV Ra, Rb, LSL #n 2. Multiplication by 2^n+1 (3,5,9,17,...) LSL ADD Rt, Rb, #n Ra, Rt, Rb ; ADD Ra, Rb, Rb, LSL #n 3. Multiplication by 2^n-1 (3,7,15,...) LSL SUB Rt, Rb, #n Ra, Rt, Rb ; RSB Ra, Rb, Rb, LSL #n 4. Multiplication by -2^n (-2, -4, -8, ...) LSL MVN Ra, Rb, #n Ra, Ra ; MOV Ra, Rb, LSL #n ; RSB Ra, Ra, #0 5. Multiplication by -2^n-1 (-3, -7, -15, ...) LSL SUB Rt, Rb, #n Ra, Rb, Rt ; SUB Ra, Rb, Rb, LSL #n Multiplication by any C = {2^n+1, 2^n-1, -2^n or -2^n-1} * 2^n Effectively this is any of the multiplications in 2 to 5 followed by a final shift. This allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) LSL Ra, Ra, #n ; (2..5) ; MOV Ra, Ra, LSL #n 4-40 S3C2410X THUMB INSTRUCTION SET GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. Thumb code ;signed_divide ; Signed divide of R1 by R0: returns quotient in R0, ; remainder in R1 ;Get abs value of R0 into R3 ASR R2, R0, #31 EOR R0, R2 SUB R3, R0, R2 ; Get 0 or -1 in R2 depending on sign of R0 ; EOR with -1 (0xFFFFFFFF) if negative ; and ADD 1 (SUB -1) to get abs value ;SUB always sets flag so go & report division by 0 if necessary BEQ divide_by_zero ;Get abs value of R1 by xoring with 0xFFFFFFFF and adding 1 if negative ASR R0, R1, #31 ; Get 0 or -1 in R3 depending on sign of R1 EOR R1, R0 ; EOR with -1 (0xFFFFFFFF) if negative SUB R1, R0 ; and ADD 1 (SUB -1) to get abs value ;Save signs (0 or -1 in R0 & R2) for later use in determining ; sign of quotient & remainder. PUSH {R0, R2} ;Justification, shift 1 bit at a time until divisor (R0 value) ; is just <= than dividend (R1 value). To do this shift dividend ; right by 1 and stop as soon as shifted value becomes >. LSR R0, R1, #1 MOV R2, R3 B %FT0 just_l LSL R2, #1 0 CMP R2, R0 BLS just_l MOV R0, #0 ; Set accumulator to 0 B %FT0 ; Branch into division loop div_l 0 LSR CMP BCC SUB ADC CMP BNE R2, #1 R1, R2 %FT0 R1, R2 R0, R0 R2, R3 div_l ; Test subtract ; If successful do a real subtract ; Shift result and add 1 if subtract succeeded ; Terminate when R2 == R3 (ie we have just ; tested subtracting the 'ones' value). 0 4-41 THUMB INSTRUCTION SET S3C2410X Now fix up the signs of the quotient (R0) and remainder (R1) POP {R2, R3} ; Get dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, R3 ; Negate if result sign = - 1 SUB R0, R3 EOR R1, R2 ; Negate remainder if dividend sign = - 1 SUB R1, R2 MOV pc, lr ARM Code signed_divide ANDS RSBMI EORS ;ip bit 31 = sign of result ;ip bit 30 = sign of a2 RSBCS ; Effectively zero a4 as top bit will be shifted out later a4, a1, #&80000000 a1, a1, #0 ip, a4, a2, ASR #32 a2, a2, #0 ;Central part is identical code to udiv (without MOV a4, #0 which comes for free as part of signed entry sequence) MOVS a3, a1 BEQ divide_by_zero just_l CMP MOVLS BLO div_l CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI MOV a2, a3 a4, a4, a4 a2, a2, a3 a3, a1 a3, a3, LSR #1 s_loop2 a1, a4 ip, ip, ASL #1 a1, a1, #0 a2, a2, #0 pc, lr a3, a2, LSR #1 a3, a3, LSL #1 s_loop ; Justification stage shifts 1 bit at a time ; NB: LSL #1 is always OK if LS succeeds 4-42 S3C2410X THUMB INSTRUCTION SET DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code. Thumb Code udiv10 MOV LSR SUB LSR ADD LSR ADD LSR ADD LSR ASL ADD ASL SUB CMP BLT ADD SUB 0 MOV ARM Code udiv10 SUB SUB ADD ADD ADD MOV ADD SUBS ADDPL ADDMI MOV a2, a1, #10 a1, a1, a1, lsr #2 a1, a1, a1, lsr #4 a1, a1, a1, lsr #8 a1, a1, a1, lsr #16 a1, a1, lsr #3 a3, a1, a1, asl #2 a2, a2, a3, asl #1 a1, a1, #1 a2, a2, #10 pc, lr ; Take argument in a1 returns quotient in a1, ; remainder in a2 pc, lr a2, a1 a3, a1, #2 a1, a3 a3, a1, #4 a1, a3 a3, a1, #8 a1, a3 a3, a1, #16 a1, a3 a1, #3 a3, a1, #2 a3, a1 a3, #1 a2, a3 a2, #10 %FT0 a1, #1 a2, #10 ; Take argument in a1 returns quotient in a1, ; remainder in a2 4-43 THUMB INSTRUCTION SET S3C2410X NOTES 4-44 S3C2410X MEMORY CONTROLLER 5 MEMORY CONTROLLER OVERVIEW The S3C2410X memory controller provides memory control signals required for external memory access. The S3C2410X has the following features: -- Little/Big endian (selectable by a software) -- Address space: 128Mbytes per bank (total 1GB/8 banks) -- Programmable access size (8/16/32-bit) for all banks except bank0 (16/32-bit) -- Total 8 memory banks Six memory banks for ROM, SRAM, etc. Remaining two memory banks for ROM, SRAM, SDRAM, etc . -- Seven fixed memory bank start address -- One flexible memory bank start address and programmable bank size -- Programmable access cycles for all memory banks -- External wait to extend the bus cycles -- Supporting self-refresh and power down mode in SDRAM \ 5-1 MEMORY CONTROLLER S3C2410X OM[1:0] = 01,10 0xFFFF_FFFF Not used 0x6000_0000 SFR Area 0x4800_0000 0x4000_0FFF BootSRAM (4KBytes) 0x4000_0000 SROM/SDRAM (nGCS7) 0x3800_0000 SROM/SDRAM (nGCS6) 0x3000_0000 SROM (nGCS5) 0x2800_0000 SROM (nGCS4) 0x2000_0000 SROM (nGCS3) 0x1800_0000 SROM (nGCS2) 0x1000_0000 SROM (nGCS1) 0x0800_0000 SROM (nGCS0) 0x0000_0000 [Not using NAND flash for boot ROM] OM[1:0] = 00 Not used SFR Area Not used SROM/SDRAM (nGCS7) SROM/SDRAM (nGCS6) SROM (nGCS5) SROM (nGCS4) SROM (nGCS3) SROM (nGCS2) SROM (nGCS1) Boot Internal SRAM (4KB) [Using NAND flash for boot ROM] 2MB/4MB/8MB/16MB /32MB/64MB/128MB 2MB/4MB/8MB/16MB /32MB/64MB/128MB 128MB Refer to Table 5-1 128MB 128MB 1GB HADDR[29:0] Accessible Region 128MB 128MB 128MB NOTES: 1. SROM means ROM or SRAM type memory. 2. SFR means Special Function Register. Figure 5-1. S3C2410X Memory Map after Reset Table 5-1. Bank 6/7 Addresses Address Bank 6 Start address 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 End address 0x301f_ffff 0x303f_ffff 0x307f_ffff 0x30ff_ffff 0x31ff_ffff 0x33ff_ffff 0x37ff_ffff 2MB 4MB 8MB 16MB 32MB 64MB 128MB Bank 7 Start address 0x3020_0000 0x3040_0000 0x3080_0000 0x3100_0000 0x3200_0000 0x3400_0000 0x3800_0000 End address 0x303f_ffff 0x307f_ffff 0x30ff_ffff 0x31ff_ffff 0x33ff_ffff 0x37ff_ffff 0x3fff_ffff NOTE: Bank 6 and 7 must have the same memory size. 5-2 S3C2410X MEMORY CONTROLLER FUNCTION DESCRIPTION BANK0 BUS WIDTH The data bus of BANK0 (nGCS0) should be configured in width as one of 16-bit and 32-bit ones. Because the BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will depend on the logic level of OM[1:0] at Reset. OM1 (Operating Mode 1) 0 0 1 1 OM0 (Operating Mode 0) 0 1 0 1 Booting ROM Data width Nand Flash Mode 16-bit 32-bit Test Mode MEMORY (SROM/SDRAM) ADDRESS PIN CONNECTIONS MEMORY ADDR. PIN A0 A1 *** S3C2410X ADDR. @ 8-bit DATA BUS S3C2410X ADDR. @ 16-bit DATA BUS S3C2410X ADDR. @ 32-bit DATA BUS A0 A1 *** A1 A2 *** A2 A3 *** 5-3 MEMORY CONTROLLER S3C2410X SDRAM BANK ADDRESS PIN CONNECTION Table 5-2. SDRAM Bank Address Configuration Base Component Memory Configuration 16Mb 16Mb Bank Size 2MB 4MB Bus Width x8 x16 x8 x16 x32 Bank Address A20 A21 ( ( ( 1M x 8 x 2banks) x 1 ea 2M x 4 x 2banks) x 2 ea 1M x 8 x 2banks) x 2 ea 2M x 4 x 2banks) x 4 ea 1M x 8 x 2banks) x 4 ea 4M x 8 x 2banks) x 1 ea 2M x 8 x 4banks) x 1 ea 2M x 16 x 2banks) x 1 ea 1M x 16 x 4banks) x 1 ea 2M x 4 x 2banks) x 8 ea 8M x 4 x 2banks) x 2 ea 4M x 4 x 4banks) x 2 ea 4M x 8 x 2banks) x 2 ea 2M x 8 x 4banks) x 2 ea 2M x 16 x 2banks) x 2 ea 1M x 16 x 4banks) x 2 ea 4M x 8 x 4banks) x 1 ea 2M x 16 x 4banks) x 1 ea 8M x 4 x 2banks) x 4 ea 4M x 4 x 4banks) x 4 ea 4M x 8 x 2banks) x 4 ea 2M x 8 x 4banks) x 4 ea 4M x 8 x 4banks) x 2 ea 2M x 16 x 4banks) x 2 ea 8M x 8 x 4banks) x 1 ea 4M x 16 x 4banks) x 1 ea 4M x 8 x 4banks) x 4 ea 8M x 8 x 4banks) x 2 ea 4M x 16 x 4banks) x 2 ea 8M x 8 x 4banks) x 4 ea (512K x 16 x 2banks) x 1 ea (512K x 16 x 2banks) x 2 ea 16Mb 64Mb 8MB x16 x32 x8 x8 x16 x16 x32 ( ( ( ( ( ( A22 A[22:21] A22 A[22:21] A23 A[23:22] A23 A[23:22] A23 A[23:22] (512K x 32 x 4banks) x 1 ea 16Mb 64Mb 16MB x32 x8 x8 x16 x16 x32 x32 x8 x16 ( ( ( ( ( ( ( 128Mb 64Mb ( ( ( ( ( ( 32MB x16 x16 x32 x32 x16 x32 x8 x16 A24 A[24:23] A24 A[24:23] 128Mb 256Mb 128Mb 256Mb 512Mb 256Mb 512Mb ( ( ( ( ( ( ( ( 64MB x32 x16 x32 x8 A[25:24] ( 16M x 8 x 4banks) x 1 ea A[26:25] 128MB x32 x8 x16 x32 ( 32M x 4 x 4banks) x 2 ea ( 16M x 8 x 4banks) x 2 ea ( 8M x 16 x 4banks) x 2 ea 5-4 S3C2410X MEMORY CONTROLLER nWAIT PIN OPERATION If the WAIT corresponding to each memory bank is enabled, the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the next clock after sampling nWAIT is high. The nWE signal have the same relation with nOE. HCLK ADDR nGCS Tacs Tacc=4 Tcos Sampling nWAIT Delayed nOE nWAIT DATA(R) Figure 5-2. S3C2410X External nWAIT Timing Diagram (Tacc=4) 5-5 MEMORY CONTROLLER S3C2410X nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the S3C2410X will respond by lowering nXBACK. If nXBACK=L, the address/data bus and memory control signals are in Hi-Z state as shown in Table 1-1. When nXBREQ is de-asserted, the nXBACK will also be de-asserted. HCLK SCLK SCKE, A[24:0] D[31:0],nGCS nOE,nWE nWBE nXBREQ ~ ~ ~ ~ ~ ~ 1CLK nXBACK Figure 5-3. S3C2410X nXBREQ/nXBACK Timing Diagram ~ ~ 5-6 S3C2410X MEMORY CONTROLLER ROM Memory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nGCSn Figure 5-4. Memory Interface with 8-bit ROM A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D8 D9 D10 D11 D12 D13 D14 D15 nWBE1 nOE nGCSn Figure 5-5. Memory Interface with 8-bit ROM x 2 5-7 MEMORY CONTROLLER S3C2410X A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D8 D9 D10 D11 D12 D13 D14 D15 nWBE1 nOE nGCSn A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D16 D17 D18 D19 D20 D21 D22 D23 nWBE2 nOE nGCSn A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D24 D25 D26 D27 D28 D29 D30 D31 nWBE3 nOE nGCSn Figure 5-6. Memory Interface with 8-bit ROM x 4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn Figure 5-7. Memory Interface with 16-bit ROM 5-8 S3C2410X MEMORY CONTROLLER SRAM Memory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0 Figure 5-8. Memory Interface with 16-bit SRAM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nWE nOE nGCSn nBE1 nBE0 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nUB nLB D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 nWE nOE nGCSn nBE3 nBE2 Figure 5-9. Memory Interface with 16-bit SRAM x 2 5-9 MEMORY CONTROLLER S3C2410X SDRAM Memory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A21 A22 DQM0 DQM1 SCKE SCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE Figure 5-10. Memory Interface with 16-bit SDRAM(8MB: 1Mb x 16 x 4banks) A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A22 A23 DQM0 DQM1 SCKE SCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRAS nSCAS nWE A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A22 A23 DQM2 DQM3 SCKE SCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 LDQM UDQM SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 nSCS0 nSRAS nSCAS nWE Figure 5-11. Memory Interface with 16-bit SDRAM (16MB: 1Mb x 16 x 4banks x 2ea) NOTE: Refer to Table 5-2 for the Bank Address configurations of SDRAM. 5-10 S3C2410X MEMORY CONTROLLER PROGRAMMABLE ACCESS CYCLE HCLK A[24:0] nGCS Tacs Tcos Tacc Tacp Tcoh Tcah nOE nWE nWBE D[31:0](R) D[31:0] (W) Tacs = 1 cycle Tcos = 1 cycle Tacc = 3 cycles Tacp = 2 cycles Tcoh = 1 cycle Tcah = 2 cycles Figure 5-12. S3C2410X nGCS Timing Diagram 5-11 MEMORY CONTROLLER S3C2410X HCLK SCKE nSCS Trp nSRAS nSCAS Trcd ADDR RA Ca Cb Cc Cd Ce BA BA BA BA BA BA BA BA A10/AP RA DATA (CL2) Da Db Dc Dd De DATA (CL3) Da Db Dc Dd De nWE DQM Bank Precharge Row Active Write Read (CL = 2, CL = 3, BL = 1) Trp = 2 cycle Trcd = 2 cycle Tcas = 2 cycle Tcp = 2 cycle Figure 5-13. S3C2410X SDRAM Timing Diagram 5-12 S3C2410X MEMORY CONTROLLER BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) Register BWSCON Address 0x48000000 R/W R/W Description Bus width & wait status control register Reset Value 0x000000 BWSCON ST7 Bit [31] Description Determine SRAM for using UB/LB for bank 7. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 7. 0 = WAIT disable 1 = WAIT enable Determine data bus width for bank 7. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved Initial state 0 WS7 DW7 ST6 [30] [29:28] [27] 0 0 0 Determine SRAM for using UB/LB for bank 6. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0 ) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 6. 0 = WAIT disable, 1 = WAIT enable Determine data bus width for bank 6. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved WS6 DW6 ST5 [26] [25:24] [23] 0 0 0 Determine SRAM for using UB/LB for bank 5. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 5. 0 = WAIT disable, 1 = WAIT enable Determine data bus width for bank 5. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved WS5 DW5 ST4 [22] [21:20] [19] 0 0 0 Determine SRAM for using UB/LB for bank 4. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 4. 0 = WAIT disable 1 = WAIT enable Determine data bus width for bank 4. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved WS4 DW4 ST3 [18] [17:16] [15] 0 0 0 Determine SRAM for using UB/LB for bank 3. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 3. 0 = WAIT disable 1 = WAIT enable Determine data bus width for bank 3. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved WS3 DW3 ST2 [14] [13:12] [11] 0 0 0 Determine SRAM for using UB/LB for bank 2. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0].) 5-13 MEMORY CONTROLLER S3C2410X BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continued) WS2 DW2 ST1 [10] [9:8] [7] Determine WAIT status for bank 2. 0 = WAIT disable 1 = WAIT enable Determine data bus width for bank 2. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved 0 0 0 Determine SRAM for using UB/LB for bank 1. 0 = Not using UB/LB (The pins are dedicated nWBE[3:0]) 1 = Using UB/LB (The pins are dedicated nBE[3:0]) Determine WAIT status for bank 1. 0 = WAIT disable, 1 = WAIT enable Determine data bus width for bank 1. 00 = 8-bit 01 = 16-bit, 10 = 32-bit 11 = reserved WS1 DW1 DW0 [6] [5:4] [2:1] 0 0 - Indicate data bus width for bank 0 (read only). 01 = 16-bit, 10 = 32-bit The states are selected by OM[1:0] pins Reserved [0] - NOTES: 1. All types of master clock in this memory controller correspond to the bus clock. For example, HCLK in SRAM is the same as the bus clock, and SCLK in SDRAM is also the same as the bus clock. In this chapter (Memory Controller), one clock means one bus clock. 2. nBE[3:0] is the 'AND' signal nWBE[3:0] and nOE. 5-14 S3C2410X MEMORY CONTROLLER BANK CONTROL REGISTER (BANKCONN: nGCS0-nGCS5) Register BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 Address 0x48000004 0x48000008 0x4800000C 0x48000010 0x48000014 0x48000018 R/W R/W R/W R/W R/W R/W R/W Description Bank 0 control register Bank 1 control register Bank 2 control register Bank 3 control register Bank 4 control register Bank 5 control register Reset Value 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 BANKCONn Tacs Bit [14:13] Description Address set-up time before nGCSn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Chip selection set-up time before nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Access cycle 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks NOTE: Initial State 00 Tcos [12:11] 00 Tacc [10:8] 111 001 = 2 clocks 011 = 4 clocks 101 = 8 clocks 111 = 14 clocks When nWAIT signal is used, Tacc 4 clocks. Tcoh [7:6] Chip selection hold time after nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Address hold time after nGCSn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Page mode access cycle @ Page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks Page mode configuration 00 = normal (1 data) 01 = 4 data 10 = 8 data 11 = 16 data 000 Tcah [5:4] 00 Tacp [3:2] 00 PMC [1:0] 00 5-15 MEMORY CONTROLLER S3C2410X BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) Register BANKCON6 BANKCON7 Address 0x4800001C 0x48000020 R/W R/W R/W Description Bank 6 control register Bank 7 control register Reset Value 0x18008 0x18008 BANKCONn MT Bit [16:15] Description Determine the memory type for bank6 and bank7. 00 = ROM or SRAM 01 = Reserved (Do not use) 10 = Reserved (Do not use) 11 = Sync. DRAM Address set-up time before nGCS 00 = 0 clock 01 = 1 clock 10 = 2 clocks Chip selection set-up time before nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks Access cycle 000 = 1 clock 010 = 3 clocks 100 = 6 clocks 110 = 10 clocks 001 = 2 clocks 011 = 4 clocks 101 = 8 clocks 111 = 14 clocks Initial State 11 Memory Type = ROM or SRAM [MT=00] (15-bit) Tacs Tcos Tacc [14:13] [12:11] [10:8] 00 11 = 4 clocks 00 11 = 4 clocks 111 Tcoh [7:6] Chip selection hold time after nOE 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks Address hold time after nGCSn 00 = 0 clock 01 = 1clock 10 = 2 clocks Page mode access cycle @ Page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks Page mode configuration 00 = normal (1 data) 10 = 8 consecutive accesses RAS to CAS delay 00 = 2 clocks 01 = 3 clocks Column address number 00 = 8-bit 01 = 9-bit 01 = 4 consecutive accesses 11 = 16 consecutive accesses 11 = 4 clocks 00 Tcah Tacp [5:4] [3:2] 00 00 PMC [1:0] 00 Memory Type = SDRAM [MT=11] (4-bit) Trcd SCAN [3:2] [1:0] 10 10 = 4 clocks 00 10= 10-bit 5-16 S3C2410X MEMORY CONTROLLER REFRESH CONTROL REGISTER Register REFRESH Address 0x48000024 R/W R/W Description SDRAM refresh control register Reset Value 0xac0000 REFRESH REFEN TREFMD Bit [23] [22] SDRAM Refresh Enable 0 = Disable Description 1 = Enable (self/auto refresh) Initial State 1 0 SDRAM Refresh Mode 0 = Auto Refresh 1 = Self Refresh In self-refresh time, the SDRAM control signals are driven to the appropriate level. SDRAM RAS pre-charge Time 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = Not support Trp Tsrc [21:20] [19:18] 10 11 SDRAM Semi Row Cycle Time 00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks SDRAM's Row_Cycle time (Trc) = Tsrc + Trp If) Trp = 3 clocks & Tsrc = 7 clocks, Trc = 3 + 7 = 10 clocks Reserved Reserved Refresh Counter [17:16] [15:11] [10:0] Not used Not used SDRAM refresh count value. Refresh period = (211-refresh_count+1)/HCLK Ex) If refresh period is 15.6 us and HCLK is 60 MHz, the refresh count is as follows: Refresh count = 211 + 1 - 60x15.6 = 1113 00 0000 0 5-17 MEMORY CONTROLLER S3C2410X BANKSIZE REGISTER Register BANKSIZE Address 0x48000028 R/W R/W Description Flexible bank size register Reset Value 0x0 BANKSIZE BURST_EN Bit [7] Description ARM core burst operation enable. 0 = Disable burst operation. 1 = Enable burst operation. Initial State 0 Reserved SCKE_EN [6] [5] Not used SDRAM power down mode enable control by SCKE 0 = SDRAM power down mode disable 1 = SDRAM power down mode enable SCLK is enabled only during SDRAM access cycle for reducing power consumption. When SDRAM is not accessed, SCLK becomes 'L' level. 0 = SCLK is always active. 1 = SCLK is active only during the access (recommended). 0 0 SCLK_EN [4] 0 Reserved BK76MAP [3] [2:0] Not used BANK6/7 memory map 010 = 128MB/128MB 000 = 32M/32M 110 = 8M/8M 100 = 2M/2M 001 = 64MB/64MB 111 = 16M/16M 101 = 4M/4M 0 010 5-18 S3C2410X MEMORY CONTROLLER SDRAM MODE REGISTER SET REGISTER (MRSR) Register MRSRB6 MRSRB7 Address 0x4800002C 0x48000030 R/W R/W R/W Description Mode register set register bank6 Mode register set register bank7 Reset Value xxx xxx MRSR Reserved WBL Bit [11:10] [9] Not used Write burst length 0: Burst (Fixed) 1: Reserved Description Initial State - x TM [8:7] Test mode 00: Mode register set (Fixed) 01, 10 and 11: Reserved CAS latency 000 = 1 clock, 010 = 2 clocks, Others: reserved Burst type 0: Sequential (Fixed) 1: Reserved Burst length 000: 1 (Fixed) Others: Reserved 011=3 clocks xx CL [6:4] xxx BT [3] x BL [2:0] xxx NOTE: MRSR register must not be reconfigured while the code is running on SDRAM. IMPORTANT NOTES In Power_OFF mode, SDRAM has to enter SDRAM self-refresh mode. 5-19 MEMORY CONTROLLER S3C2410X NOTES 5-20 S3C2410X NAND FLASH CONTROLLER 6 NAND FLASH CONTROLLER OVERVIEW Recently, a NOR flash memory gets high in price while an SDRAM and a NAND flash memory get moderate, motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM. S3C2410X boot code can be executed on an external NAND flash memory. In order to support NAND flash boot loader, the S3C2410X is equipped with an internal SRAM buffer called `Steppingstone'. When booting, the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed. Generally, the boot code will copy NAND flash content to SDRAM. Using hardware ECC, the NAND flash data validity will be checked. Upon the completion of the copy, the main program will be executed on the SDRAM. FEATURES * * * * NAND Flash mode: Support read/erase/program NAND flash memory Auto boot mode : The boot code is transferred into Steppingstone after reset. After the transfer, the boot code will be executed on the Steppingstone. Hardware ECC detecting block (for hardware detecting and software correcting) The Steppingstone 4-KB internal SRAM buffer can be used for another purpose after NAND flash booting. 6-1 NAND FLASH CONTROLLER S3C2410X BLOCK DIAGRAM System Bus Buffer Control InternalL Buffer (4KB) Register Bank Contrlol State Machine ECC Encoder/ Decoder NAND Flash Interface CLE ALE nCE nRE nWE R/nB I/O0~I/O7 Figure 6-1. NAND Flash Controller Block Diagram OPERATION SCHEME CPU Access (Boot Code) Steppingstone (4 KB Buffer) Auto Boot Mode User Access Special Function Registers NAND Flash Controller NAND Flash Memory NAND Flash Mode Figure 6-2. NAND Flash Operation Scheme 6-2 S3C2410X NAND FLASH CONTROLLER AUTO BOOT MODE SEQUENCE 1. Reset is completed. 2. When the auto boot mode is enabled, the first 4 KBytes of NAND flash memory is copied onto Steppingstone 4-KB internal buffer. 3. The Steppingstone is mapped to nGCS0. 4. CPU starts to execute the boot code on the Steppingstone 4-KB internal buffer. NOTE In the auto boot mode, ECC is not checked. So, The first 4 KBytes of NAND flash should have no bit error. NAND FLASH MODE CONFIGURATION 1. Set NAND flash configuration by NFCONF register. 2. Write NAND flash command onto NFCMD register. 3. Write NAND flash address onto NFADDR register. 4. Read/Write data while checking NAND flash status by NFSTAT register. R/nB signal should be checked before read operation or after program operation. NAND FLASH MEMORY TIMING HCLK CLE/ALE nWE TACLS TWRPH0 TWRPH1 Figure 6-3. TACLS=0, TWRPH0=1, TWRPH1=0 6-3 NAND FLASH CONTROLLER S3C2410X PIN CONFIGURATION D[7:0] CLE ALE nFCE nFRE nFWE nWAIT : Data/Command/Address In/Out Port (shared with the data bus) : Command Latch Enable (Output) : Address Latch Enable (Output) : NAND Flash Chip Enable (Output) : NAND Flash Read Enable (Output) : NAND Flash Write Enable (Output) : NAND Flash Ready/nBusy (Input) BOOT AND NAND FLASH CONFIGURATIONS 1. OM[1:0] = 00b : Enable NAND Flash controller auto boot mode 2. NAND Flash memory page size should be 512Bytes. 3. NCON : NAND Flash memory address step selection 0 : 3 Step addressing 1 : 4 Step addressing 512-BYTE ECC PARITY CODE ASSIGNMENT TABLE DATA7 ECC0 ECC1 ECC2 P64 P1024 P4 DATA6 P64' P1024' P4' DATA5 P32 P512 P2 DATA4 P32' P512' P2' DATA3 P16 P256 P1 DATA2 P16' P256' P1' DATA1 P8 P128 P2048 DATA0 P8' P128' P2048' S3C2410 generates 512-Byte ECC Parity Code during Write/Read operation. ECC Parity Code consists of 3 Bytes per 512-Byte data. 24-bit ECC Parity Code = 18-bit Line parity + 6-bit Column Parity ECC generator block executes the followings: 1. When MCU writes data to NAND, the ECC generator block generates ECC code. 2. When MCU reads data from NAND, the ECC generator block generates ECC code and compares it with prewritten ECC code. 6-4 S3C2410X NAND FLASH CONTROLLER NAND FLASH MEMORY MAPPING 0xFFFF_FFFF 0x6000_0000 Not Used SFR Area Not Used SFR Area Not Used SDRAM (BANK7, nGCS7) SDRAM (BANK6, nGCS6) SROM (BANK5, nGCS5) SROM (BANK4, nGCS4) SROM (BANK3, nGCS3) SROM (BANK2, nGCS2) SROM (BANK1, nGCS1) BootSRAM (4KBytes) OM[1:0] == 00 a) Using NAND flash for booting ROM 0x4800_0000 0x4000_0FFF 0x4000_0000 0x3800_0000 SDRAM (BANK6, nGCS6) 0x3000_0000 0x2800_0000 SROM (BANK4, nGCS4) 0x2000_0000 0x1800_0000 0x1000_0000 SROM (BANK1, nGCS1) 0x0800_0000 0x0000_0000 OM[1:0] == 01, 10 a) Not using NAND flash for booting ROM SROM (BANK0, nGCS0) SROM (BANK3, nGCS3) SROM (BANK2, nGCS2) SROM (BANK5, nGCS5) BootSRAM (4KBytes) SDRAM (BANK7, nGCS7) NOTE: SFR means Special Function Register. Figure 6-4. NAND Flash Memory Mapping 6-5 NAND FLASH CONTROLLER S3C2410X SPECIAL FUNCTION REGISTERS NAND FLASH CONFIGURATION (NFCONF) REGISTER Register NFCONF Address 0x4E000000 R/W R/W Description NAND Flash configuration Reset Value - NFCONF Enable/Disable Bit [15] Description NAND Flash controller enable/disable 0 = Disable NAND Flash Controller 1 = Enable NAND Flash Controller After auto-boot, this bit is cleared to 0 automatically. For the access to the NAND flash memory, this bit must be set. Initial State 0 Reserved Initialize ECC [14:13] [12] Reserved Initialize ECC decoder/encoder 0 : Not initialize ECC 1 : Initialize ECC (S3C2410 supports only 512-Byte ECC checking, so it is required to set ECC initialized per 512 Bytes.)- - 0 NAND Flash Memory chip enable [11] NAND Flash Memory nFCE control 0 : NAND flash nFCE = L (active) 1 : NAND flash nFCE = H (inactive) (After auto-boot, nFCE will be inactive.) - TACLS Reserved TWRPH0 Reserved TWRPH1 [10:8] [7] [6:4] [3] [2:0] CLE & ALE duration setting value (0~7) Duration = HCLK * (TACLS + 1) Reserved TWRPH0 duration setting value (0~7) Duration = HCLK * (TWRPH0 + 1) Reserved TWRPH1 duration setting value (0~7) Duration = HCLK * (TWRPH1 + 1) - 0 - 0 6-6 S3C2410X NAND FLASH CONTROLLER NAND FLASH COMMAND SET (NFCMD) REGISTER Register NFCMD Address 0x4E000004 R/W R/W Description NAND flash command set register Reset Value - NFCMD Reserved Command Bit [15:8] [7:0] Reserved Description NAND Flash memory command value Initial State - 0x00 NAND FLASH ADDRESS SET (NFADDR) REGISTER Register NFADDR Address 0x4E000008 R/W R/W Description NAND flash address set register Reset Value - NFADDR Reserved Address Bit [15:8] [7:0] Reserved Description NAND flash memory address value Initial State - 0x00 NAND FLASH DATA (NFDATA) REGISTER Register NFDATA Address 0x4E00000C R/W R/W Description NAND flash data register Reset Value - NFDATA Reserved Data Bit [15:8] [7:0] Reserved Description NAND Flash read/program data value In case of write: Programming data In case of read: Read data. Initial State - - 6-7 NAND FLASH CONTROLLER S3C2410X NAND FLASH OPERATION STATUS (NFSTAT) REGISTER Register NFSTAT Address 0x4E000010 R/W R Description NAND Flash operation status Reset Value - NFSTAT Reserved RnB Bit [16:1] [0] Reserved Description NAND Flash memory ready/busy status. (This signal is checked through R/nB pin.) 0 = NAND Flash memory busy 1 = NAND Flash memory ready to operate Initial State - - NAND FLASH ECC (NFECC) REGISTER Register NFECC Address 0x4E000014 R/W R Description NAND Flash ECC (Error Correction Code) register Reset Value - NFECC ECC2 ECC1 ECC0 Bit [23:16] [15:8] [7:0] Description Error Correction Code #2 Error Correction Code #1 Error Correction Code #0 Initial State - - - Known Problems * * Problem : NAND flash controller can't be accessed by DMA. Solution : Instead of DMA, use LDM/STM Instructions like our boot loader example code. 6-8 S3C2410X CLOCK & POWER MANAGEMENT 7 CLOCK & POWER MANAGEMENT OVERVIEW The clock & power management block consists of three parts: clock control, USB control, and power control. The Clock control logic in S3C2410X can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals. The S3C2410X has two Phase Locked Loops (PLLs): one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz). The clock control logic can make slow clocks without PLL and connect/disconnect the clock to each peripheral block by software, which will reduce the power consumption. For the power control logic, the S3C2410X has various power management schemes to keep optimal power consumption for a given task. The power management block in the S3C2410X can activate four modes: NORMAL mode, SLOW mode, IDLE mode, and Power-OFF mode. NORMAL mode: the block supplies clocks to CPU as well as all peripherals in the S3C2410X. In this mode, the power consumption will be maximized when all peripherals are turned on. It allows the user to control the operation of peripherals by software. For example, if a timer is not needed, the user can disconnect the clock to the timer to reduce power consumption. SLOW mode: Non-PLL mode. Unlike the Normal mode, the Slow mode uses an external clock (XTIpll or EXTCLK) directly as FCLK in the S3C2410X without PLL. In this mode, the power consumption depends on the frequency of the external clock only. The power consumption due to PLL is excluded. IDLE mode: the block disconnects clocks (FCLK) only to the CPU core while it supplies clocks to all other peripherals. The IDLE mode results in reduced power consumption due to CPU core. Any interrupt request to CPU can be woken up from the Idle mode. Power-OFF mode: the block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the Power-OFF mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off. In the Power-OFF mode, the second power supply source for the CPU and internal logics will be turned off. The wakeup from Power-OFF mode can be issued by the EINT[15:0] or by RTC alarm interrupt. 7-1 CLOCK & POWER MANAGEMENT S3C2410X FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7-1 shows a block diagram of the clock architecture. The main clock source comes from an external crystal (XTIpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier), which is connected to an external crystal, and also has two PLLs (Phase-Locked-Loop), which generate the high frequency clock required in the S3C2410X. CLOCK SOURCE SELECTION Table 7-1 shows the relationship between the combination of mode control pins (OM3 and OM2) and the selection of source clock for the S3C2410X. The OM[3:2] status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET. Table 7-1. Clock Source Selection at Boot-Up Mode OM[3:2] 00 01 10 11 MPLL State On On On On UPLL State On On On On Main Clock source Crystal Crystal EXTCLK EXTCLK USB Clock Source Crystal EXTCLK Crystal EXTCLK NOTES: 1. Although the MPLL starts just after a reset, the MPLL output (Mpll) is not used as the system clock until the software writes valid settings to the MPLLCON register. Before this valid setting, the clock from external crystal or EXTCLK source will be used as the system clock directly. Even if the user does not want to change the default value of MPLLCON register, the user should write the same value into MPLLCON register. 2. OM[3:2] is used to determine a test mode when OM[1:0] is 11. 7-2 S3C2410X CLOCK & POWER MANAGEMENT OM[3:2] XTIpll XTOpll EXTCLK OSC P[5:0] M[7:0] S[1:0] MPLL Mpll CLKCNTL FCLK HDIVN PDIVN MPLL CLK UPLL CLK HCLK PCLK FCLK Control Signal USBCNTL Upll UPLL CLKOUT F H P POWCNTL P[5:0] M[7:0] S[1:0] Power Management Block Test mode OM[1:0] UCLK HCLK PCLK Nand Flash Controller H_USB H_Nand FCLK Memory Controller ARM920T USB Host I/F Interrupt Controller H_LCD LCD Controller TIC ExtMaster Bus Controller Arbitration DMA 4ch WDT I 2S P_I C 2 2 SDI P_SDI P_GPIO GPIO ADC P_ADC P_RTC RTC UART(0,1,2) P_UART P_SPI SPI(0,1) P_PWM PWM USB Device 2 P_I C IC P_USB Figure 7-1. Clock Generator Block Diagram 7-3 CLOCK & POWER MANAGEMENT S3C2410X PHASE LOCKED LOOP (PLL) The MPLL within the clock generator, as a circuit, synchronizes an output signal with a reference input signal in frequency and phase. In this application, it includes the following basic blocks as shown in Figure 7-2: the Voltage Controlled Oscillator (VCO) to generate the output frequency proportional to input DC voltage, the divider P to divide the input frequency (Fin) by p, the divider M to divide the VCO output frequency by m which is input to Phase Frequency Detector (PFD), the divider S to divide the VCO output frequency by s which is Mpll (the output frequency from MPLL block), the phase difference detector, the charge pump, and the loop filter. The output clock frequency Mpll is related to the reference input clock frequency Fin by the following equation: Mpll = (m * Fin) / (p * 2s) m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2 The UPLL within the clock generator is the same as the MPLL in every aspect. The following sections describe the operation of the PLL, including the phase difference detector, the charge pump, the Voltage controlled oscillator (VCO), and the loop filter. Phase Difference Detector (PFD) The PFD monitors the phase difference between Fref and Fvco, and generates a control signal (tracking signal) when it detects a difference. The Fref means the reference frequency as shown in the Figure 7-2. Charge Pump (PUMP) The charge pump converts PFD control signals into a proportional charge in voltage across the external filter that drives the VCO. Loop Filter The control signal, which the PFD generates for the charge pump, may generate large excursions (ripples) each time the Fvco is compared to the Fref. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. The filter is typically a single-pole RC filter with a resistor and a capacitor. Voltage Controlled Oscillator (VCO) The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage. When the Fvco matches Fref in terms of frequency as well as phase, the PFD stops sending control signals to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the PLL remains fixed onto the system clock. Usual Conditions for PLL & Clock Generator PLL & Clock Generator generally uses the following conditions. Loop filter capacitance External X-tal frequency External capacitance used for X-tal 5 pF 10 - 20 MHz (note) 15 - 22 pF NOTES: 1. The value could be changed. 2. FCLK must be more than three times X-tal or EXTCLK (FCLK 3X-tal or 3EXTCLK) 7-4 S3C2410X CLOCK & POWER MANAGEMENT Fin Divider P Fref PFD PUMP R C Fvco Divider M Loop Filter P[5:0] MPLLCAP, UPLLCAP 5 pF VCO Internal External M[7:0] S[1:0] Divider S MPLL,UPLL Figure 7-2. PLL (Phase-Locked Loop) Block Diagram VDD EXTCLK External OSC VDD XTIpll XTIpll EXTCLK XTOpll XTOpll a) X-TAL Oscillation (OM[3:2]=00) b) External Clock Source (OM[3:2]=11) Figure 7-3. Main Oscillator Circuit Examples 7-5 CLOCK & POWER MANAGEMENT S3C2410X CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK). When PLL is configured to a new frequency value, the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time. The clock control logic is also activated at power-on reset and wakeup from power-down mode. Power-On Reset (XTIpll) Figure 7-4 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the stabilization of OSC (XTIpll) clock, the PLL starts to operate according to the default PLL configuration. However, PLL is commonly known to be unstable after power-on reset, so Fin is fed directly to FCLK instead of the Mpll (PLL output) before the software newly configures the PLLCON. Even if the user does not want to change the default value of PLLCON register after reset, the user should write the same value into PLLCON register by software. The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency. FCLK can be configured as PLL output (Mpll) immediately after lock time. Power PLL can operate after OM[3:2] is latched. nRESET OSC (XTIpll) PLL is configured by S/W first time. Clock Disable Lock Time VCO is adapted to new clock frequency. VCO output FCLK The logic operates by XTIpll FCLK is new frequency Figure 7-4. Power-On Reset Sequence (when the external clock source is a crystal oscillator) 7-6 S3C2410X CLOCK & POWER MANAGEMENT Change PLL Settings In Normal Operation Mode During the operation of the S3C2410X in NORMAL mode, the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted. During the lock time, the clock is not supplied to the internal blocks in the S3C2410X. Figure 7-5 shows the timing diagram. Mpll PMS setting PLL Lock-time FCLK It changes to new PLL clock after automatic lock time. Figure 7-5. Changing Slow Clock by Setting PMS Value USB Clock Control USB host interface and USB device interface needs 48Mhz clock. In the S3C2410X, the USB dedicated PLL (UPLL) generates 48Mhz for USB. UCLK does not fed until the PLL (UPLL) is configured. Condition After reset After configuring UPLL UPLL is turned off by CLKSLOW register UPLL is turned on by CLKSLOW register L UCLK State XTlpll or EXTCLK : during PLL lock time 48MHz: after PLL lock time XTlpll or EXTCLK 48MHz Off On UPLL State On On 7-7 CLOCK & POWER MANAGEMENT S3C2410X FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and the USB host block. PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI. The S3C2410X supports selection of Dividing Ratio between FCLK, HLCK and PCLK. This ratio is determined by HDIVN and PDIVN of CLKDIVN control register. HDIVN 0 0 1 1 PDIVN 0 1 0 1 FCLK FCLK FCLK FCLK FCLK HCLK FCLK FCLK FCLK / 2 FCLK / 2 PCLK FCLK FCLK / 2 FCLK / 2 FCLK / 4 Divide Ratio 1:1:1 (Default) 1:1:2 1:2:2 1:2:4 (recommended) After setting PMS value, it is required to set CLKDIVN register. The setting value of CLKDIVN will be valid after PLL lock time. The value is also available for reset and changing Power Management Mode. The setting value can also be valid after 1.5 HCLK. Only, 1HCLK can validate the value of CLKDIVN register changed from Default (1:1:1) to other Divide Ratio (1:1:2, 1:2:2 and 1:2:4) FCLK CLKDIVN HCLK PCLK 1 HCLK 1.5 HCLK 1.5 HCLK 0x00000000 0x00000001(1:1:2) 0x00000003 (1:2:4) 0x00000000 (1:1:1) Figure 7-6. Changing CLKDIVN Register Value NOTES 1. CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK. 2. If HDIVN=1, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions. MMU_SetAsyncBusMode mrc p15,0,r0,c1,c0,0 orr r0,r0,#R1_nF:OR:R1_iA mcr p15,0,r0,c1,c0,0 If HDIVN=1 and the CPU bus mode is the fast bus mode, the CPU will operate by the HCLK. This feature can be used to change the CPU frequency as a half without affecting the HCLK and PCLK. 7-8 S3C2410X CLOCK & POWER MANAGEMENT POWER MANAGEMENT The power management block controls the system clocks by software for the reduction of power consumption in the S3C2410X. These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals. Figure 7-7 shows the clock distribution of the S3C2410X. The S3C2410X has four power modes. The following section describes each power management mode. The transition between the modes is not allowed freely. For available transitions among the modes, see Figure 7-8. Clock Control Register ARM920T MEMCNTL WDT SPI FCLK HCLK Input Clock INTCNTL PWM BUSCNTL I2C ARB/DMA SDI ExtMaster Power Management PCLK UCLK (48 MHz) FCLK defination If SLOW mode FCLK = input clock/divider ratio If Normal mode (P, M & S value) FCLK = MPLL clock (Mpll) LCDCNTL ADC UART Nand Flash Controller I2S USB Host I/F GPIO RTC USB Device Figure 7-7. The Clock Distribution Block Diagram 7-9 CLOCK & POWER MANAGEMENT S3C2410X IDLE_BIT=1 IDLE Interrupts, EINT[0:23], RTC alarm RESET NORMAL (SLOW_BIT=0) EINT[15:0], RTC alarm SLOW (SLOW_BIT=1) POWER_OFF BIT=1 POWER_OFF Figure 7-8. Power Management State Diagram Table 7-2. Clock and Power State in Each Power Mode Mode NORMAL IDLE SLOW POWER_OFF ARM920T O X O OFF Power AHB Modules (1) Management /WDT O O O OFF O O O GPIO SEL SEL SEL 32.768kHz RTC clock O O O O APB Modules (2) & USBH/LCD/NAND SEL SEL SEL OFF Wait for wake- Previous up event state NOTES: 1. USB host,LCD, and NAND are excluded. 2. WDT is excluded. RTC interface for CPU access is included. 3. SEL : selectable(O,X), O : enable , X : disable OFF: power is turned off 7-10 S3C2410X CLOCK & POWER MANAGEMENT NORMAL Mode In normal mode, all peripherals and the basic blocks including power management block, the CPU core, the bus controller, the memory controller, the interrupt controller, DMA, and the external master may operate fully. But, the clock to each peripheral, except the basic blocks, can be stopped selectively by software to reduce the power consumption. IDLE Mode In IDLE mode, the clock to the CPU core is stopped except the bus controller, the memory controller, the interrupt controller, and the power management block. To exit the IDLE mode, EINT[23:0], or RTC alarm interrupt, or the other interrupts should be activated. (EINT is not available until GPIO block is turned on). SLOW Mode (Non-PLL Mode) Power consumption can be reduced in the SLOW mode by applying a slow clock and excluding the power consumption from the PLL. The FCLK is the frequency of divide_by_n of the input clock (XTIpll or EXTCLK) without PLL. The divider ratio is determined by SLOW_VAL in the CLKSLOW control register and CLKDIVN control register. Table 7-3. CLKSLOW and CLKDIVN Register Settings for SLOW Clock SLOW_VAL FCLK HCLK 1/1 Option (HDIVN=0) 000 001 010 011 100 101 110 111 EXTCLK or XTIpll / 1 EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 6 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 10 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 14 EXTCLK or XTIpll / 1 EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 6 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 10 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 14 1/2 Option (HDIVN=1) EXTCLK or XTIpll / 2 EXTCLK or XTIpll / 4 EXTCLK or XTIpll / 8 EXTCLK or XTIpll / 12 EXTCLK or XTIpll / 16 EXTCLK or XTIpll / 20 EXTCLK or XTIpll / 24 EXTCLK or XTIpll / 28 PCLK 1/1 Option (PDIVN=0) HCLK HCLK HCLK HCLK HCLK HCLK HCLK HCLK 1/2 Option (PDIVN=1) HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 HCLK / 2 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz UCLK In SLOW mode, PLL will be turned off to reduce the PLL power consumption. When the PLL is turned off in the SLOW mode and the user changes power mode from SLOW mode to NORMAL mode, the PLL needs clock stabilization time (PLL lock time). This PLL stabilization time is automatically inserted by the internal logic with lock time count register. The PLL stability time will take 150us after the PLL is turned on. During PLL lock time, the FCLK becomes SLOW clock. 7-11 CLOCK & POWER MANAGEMENT S3C2410X Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW clock is generated during the SLOW mode. Figure 7-11 shows the timing diagram. Mpll SLOW_BIT MPLL_OFF FCLK Divided external clock It changes to PLL clock after slow mode off Slow mode enable Slow mode disable Figure 7-9. Issuing Exit_from_Slow_mode Command in PLL on State If the user switches from SLOW mode to Normal mode by disabling the SLOW_BIT in the CLKSLOW register after PLL lock time, the frequency is changed just after SLOW mode is disabled. Figure 7-12 shows the timing diagram. Software lock time Mpll SLOW_BIT MPLL_OFF FCLK Divided OSC clock It changes to PLL clock after slow mode off Slow mode enable PLL off Slow mode disable PLL on Figure 7-10. Issuing Exit_from_Slow_mode Command After Lock Time 7-12 S3C2410X CLOCK & POWER MANAGEMENT If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit simultaneously in the CLKSLOW register, the frequency is changed just after the PLL lock time. Figure 7-13 shows the timing diagram. Hardware lock time Mpll SLOW_BIT MPLL_OFF FCLK Divided OSC clock It changes to PLL clock after lock time automatically Slow mode enable PLL off Slow mode disable PLL on Figure 7-11. Issuing Exit_from_Slow_mode Command and the Instant PLL_on Command Simultaneously 7-13 CLOCK & POWER MANAGEMENT S3C2410X Power_OFF Mode The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the Power-OFF mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off. In the Power-OFF mode, the second power supply source for the CPU and internal logics will be turned off. The wakeup from Power-OFF mode can be issued by the EINT[15:0] or by RTC alarm interrupt. Procedure to Enter Power_OFF mode 1. Set the GPIO configuration adequate for Power_OFF mode. 2. Mask all interrupts in the INTMSK register. 3. Configure the wake-up sources properly including RTC alarm. The bit of EINTMASK corresponding to the wake-up source has not to be masked in order to let the corresponding bit of SRCPND or EINTPEND set. Although a wake-up source is issued and the corresponding bit of EINTMASK is masked, the wake-up will occur and the corresponding bit of SRCPND or EINTPEND will not be set. 4. Set USB pads as suspend mode. (MISCCR[13:12]=11b) 5. Save some meaning values into GSTATUS3,4 register. These register are preserved during Power_OFF mode. 6. Configure MISCCR[1:0] for the pull-up resisters on the data bus,D[31:0]. If there is an external BUS holder, such as 74LVCH162245, turn off the pull-up resistors. If not, turn on the pull-up resistors 7. Stop LCD by clearing LCDCON1.ENVID bit. 8. Read rREFRESH and rCLKCON registers in order to fill the TLB. 9. Let SDRAM enter the self-refresh mode by setting the REFRESH[22]=1b. 10. Wait until SDRAM self-refresh is effective. 11. Set MISCCR[19:17]=111b to make SDRAM signals(SCLK0,SCLK1 and SCKE) protected during Power_OFF mode 12. Set the Power_OFF mode bit in the CLKCON register. 7-14 S3C2410X CLOCK & POWER MANAGEMENT Procedure to Wake-up from Power_OFF mode 1. The internal reset signal will be asserted if one of the wake-up sources is issued. This reset duration is determined by the internal 16-bit counter logic and the reset assertion time is calculated as tRST = (65535 / XTAL_frequency). 2. Check GSTATUS2[2] in order to know whether or not the power-up is caused by the wake-up from Power_OFF mode. 3. Release the SDRAM signal protection by setting MISCCR[19:17]=000b. 4. Configure the SDRAM memory controller. 5. Wait until the SDRAM self-refresh is released. Mostly SDRAM needs the refresh cycle of all SDRAM row. 6. The information in GSTATUS3,4 can be used for user's own purpose because the value in GSTATUS3,4 has been preserved during Power_OFF mode. 7. - For EINT[3:0], check the SRCPND register. - For EINT[15:4], check the EINTPEND instead of SRCPND (SRCPND will not be set although some bits of EINTPEND are set.). - For alarm wake-up, check the RTC time because the RTC bit of SRCPND isn't set at the alarm wake-up. - If there was the nBATT_FLT assertion during POWER_OFF mode, the corresponding bit of SRCPND has been set. Pin States in Power_OFF Mode The pin state of the Power_OFF mode is as follows; Pin Type GPIO output pin GPIO input pin GPIO bi-directional pin Function output pin Function input pin Pin Example GPB0: output GPB0: input GPG6:SPIMOSI nGCS0 nWAIT Input Input Output (the last output level is held.) Input Pin States in Power_OFF Mode Output ( GPIO data register value is used.) 7-15 CLOCK & POWER MANAGEMENT S3C2410X Power Control of VDDi and VDDiarm In Power_OFF mode, only VDDi and VDDiarm will be turned off, which is controlled by PWREN pin. If PWREN signal is active(H), VDDi and VDDiarm are supplied by an external voltage regulator. If PWREN pin is inactive (L), the VDDi and VDDiarm are turned off. NOTE Although VDDi, VDDiarm, VDDi_MPLL and VDDi_UPLL may be turned off, the other power pins have to be supplied. 1.8V Regulator 1.8V EN PWREN 1.8V Power VDDalive S3C2410X RTC Alarm VDDi VDDiarm VDDi_MPLL VDDi_UPLL Power CTRL (Alive Block) EINT RTC External Interrupt Core & Peripherals I/O 3.3V Power Figure 7-12. Power-OFF Mode 7-16 S3C2410X CLOCK & POWER MANAGEMENT Signaling EINT[15:0] for Wakeup The S3C2410X can be woken up from Power_OFF mode only if the following conditions are met. a) Level signals (H or L) or edge signals (rising or falling or both) are asserted on EINTn input pin. b) The EINTn pin has to be configured as EINT in the GPIO control register. c) nBATT_FLT pin has to be H level. It is important to configure the EINTn in the GPIO control register as an external interrupt pins, considering the condition a) above. Just after the wake-up, the corresponding EINTn pin will not be used for wakeup. This means that the pin can be used as an external interrupt request pin again. Entering IDLE Mode If CLKCON[2] is set to 1 to enter the IDLE mode, the S3C2410X will enter IDLE mode after some delay (until the power control logic receives ACK signal from the CPU wrapper). PLL On/Off The PLL can only be turned off for low power consumption in slow mode. If the PLL is turned off in any other mode, MCU operation is not guaranteed. When the processor is in SLOW mode and tries to change its state into other state with the PLL turned on, then SLOW_BIT should be clear to move to another state after PLL stabilization Pull-up Resistors on the Data Bus and Power_OFF Mode In Power_OFF mode, the data bus (D[31:0] or D[15:0] ) is in Hi-z state. But, because of the characteristics of I/O pad, the data bus pull-up resistors have to be turned on for low power consumption in Power_OFF mode. D[31:0] pin pull-up resistors can be controlled by the GPIO control register (MISCCR). However, if there is an external bus holder, such as 74LVCH162245, on the data bus, turning off the data bus pull-up resistors will be reduce power consumption. 7-17 CLOCK & POWER MANAGEMENT S3C2410X Output Port State and Power_OFF Mode The output port should have a proper logic level in power off mode, which makes the current consumption minimized. If there is no load on an output port pin, H level is preferred. If output is L, the current will be consumed through the internal parasitic resistance; if the output is H, the current will not be consumed. For an output port, the current consumption can be reduced if the output state is H. Battery Fault Signal(nBATT_FLT) There are two functions in nBATT_FLT pin as follows; -- When CPU is not in Power-OFF mode, nBATT_FLT pin will cause the interrupt request. The interrupt attribute of the nBATT_FLT is L-level triggered. -- While CPU is in Power-OFF mode, assertion of the nBATT_FLT will prohibit the wake up from the powerdown mode. So, Any wake-up source will be masked if nBATT_FLT is asserted, which is protecting the system malfunction of the low battery capacity ADC Power Down The ADC has an additional power-down bit in ADCCON. If the S3C2410X enters the Power_OFF mode, the ADC should enter its own power-down mode. S/W Work-Around After 'wake-up' from the Power_OFF mode by RTC_ALARM, the RTC source pending bit of the SRCPND register is not set. So, the ALARM date has to be checked after the wake-up from Power_OFF mode. 7-18 S3C2410X CLOCK & POWER MANAGEMENT CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER (LOCKTIME) Register LOCKTIME Address 0x4C000000 R/W R/W Description PLL lock time count register Reset Value 0x00FFFFFF LOCKTIME U_LTIME M_LTIME Bit [23:12] [11:0] Description UPLL lock time count value for UCLK. (U_LTIME > 150uS) MPLL lock time count value for FCLK, HCLK, and PCLK (M_LTIME > 150uS) Initial State 0xFFF 0xFFF PLL Control Register (MPLLCON and UPLLCON) Mpll = (m * Fin) / (p * 2s) m = (MDIV + 8), p = (PDIV + 2), s = SDIV PLL Value Selection Guide 1. Fout = m * Fin / (p*2^s), Fvco = m * Fin / p where : m=MDIV+8, p=PDIV+2, s=SDIV 2. Fin/(25*p) < 28.449e6/m < Fin/(10*p) 3. 0.7 < 3.373/sqrt(m) < 1.8 4. 160e6 Fvco 400e6 5. 20e6 Fout 300e6 ( The max. Fout of the PLL itself is 300Mhz ) 6. FCLK 3X-tal or 3EXTCLK NOTE: Although there is the rule for choosing PLL value, we recommend only the values in the PLL value recommendation table. If you have to use another value, please contact us. Register MPLLCON UPLLCON PLLCON MDIV PDIV SDIV Address 0x4C000004 0x4C000008 Bit [19:12] [9:4] [1:0] R/W R/W R/W Description MPLL configuration register UPLL configuration register Description Main divider control Pre-divider control Post divider control Reset Value 0x0005C080 0x00028080 Initial State 0x5C / 0x28 0x08 / 0x08 0x0 / 0x0 NOTE: When you set MPLL&UPLL values simultaneously, set MPLL value first and then UPLL value. 7-19 CLOCK & POWER MANAGEMENT S3C2410X PLL VALUE SELECTION TABLE It is not easy to find a proper PLL value. So, We recommend referring to the following PLL value recommendation table. Input Frequency 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00Mhz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz 12.00MHz Output Frequency 11.289MHz 16.934MHz 22.50MHz 33.75MHz 45.00MHz 50.70MHz 48.00Mhz (note) 56.25MHz 67.50MHz 79.00MHz 84.75MHz 90.00MHz 101.25MHz 113.00MHz 118.50MHz 124.00MHz 135.00MHz 147.00MHz 152.00MHz 158.00MHz 170.00MHz 180.00MHz 186.00MHz 192.00MHz 202.80MHz MDIV N/A N/A N/A 82 (0x52) 82 (0x52) 161 (0xa1) 120 (0x78) 142 (0x8e) 82 (0x52) 71 (0x47) 105 (0x69) 112 (0x70) 127 (0x7f) 105 (0x69) 150 (0x96) 116 (0x74) 82 (0x52) 90 (0x5a) 68 (0x44) 71 (0x47) 77 (0x4d) 82 (0x52) 85 (0x55) 88 (0x58) 161 (0xa1) PDIV N/A N/A N/A 2 1 3 2 2 2 1 2 2 2 1 2 1 2 2 1 1 1 1 1 1 3 SDIV N/A N/A N/A 3 3 3 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 NOTE: The 48.00Mhz output is used for UPLLCON register. 7-20 S3C2410X CLOCK & POWER MANAGEMENT CLOCK CONTROL REGISTER (CLKCON) Register CLKCON Address 0x4C00000C R/W R/W Description Clock generator control register Reset Value 0x7FFF0 CLKCON SPI IIS IIC ADC(&Touch Screen) RTC Bit [18] [17] [16] [15] [14] GPIO UART2 UART1 UART0 SDI PWMTIMER USB device USB host LCDC NAND Flash Controller POWER-OFF IDLE BIT Reserved SM_BIT [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description Control PCLK into SPI block. 0 = Disable, 1 = Enable Control PCLK into IIS block. 0 = Disable, 1 = Enable Control PCLK into IIC block. 0 = Disable, 1 = Enable Control PCLK into ADC block. 0 = Disable, 1 = Enable Control PCLK into RTC control block. Even if this bit is cleared to 0, RTC timer is alive. 0 = Disable, 1 = Enable Control PCLK into GPIO block. 0 = Disable, 1 = Enable Control PCLK into UART2 block. 0 = Disable, 1 = Enable Control PCLK into UART1 block. 0 = Disable, 1 = Enable Control PCLK into UART0 block. 0 = Disable, 1 = Enable Control PCLK into SDI interface block. 0 = Disable, 1 = Enable Control PCLK into PWMTIMER block. 0 = Disable, 1 = Enable Control PCLK into USB device block. 0 = Disable, 1 = Enable Control HCLK into USB host block. 0 = Disable, 1 = Enable Control HCLK into LCDC block. 0 = Disable, 1 = Enable Control HCLK into NAND Flash Controller block. 0 = Disable, 1 = Enable Control Power Off mode of S3C2410. 0 = Disable, 1 = Transition to Power_OFF mode Enter IDLE mode. This bit is not cleared automatically. 0 = Disable, 1 = Transition to IDLE mode Reserved SPECIAL mode. '0' is recommended normally. This bit can be used to enter SPECIAL mode in only the special condition, OM3=1 & wake-up by nRESET. Please contact us to use this bit. Initial State 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 7-21 CLOCK & POWER MANAGEMENT S3C2410X CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register CLKSLOW Address 0x4C000010 R/W R/W Description Slow clock control register Reset Value 0x00000004 CLKSLOW UCLK_ON Bit [7] Description 0: UCLK ON (UPLL is also turned on and the UPLL lock time is inserted automatically.) 1: UCLK OFF (UPLL is also turned off.) Reserved 0 : PLL is turned on. After PLL stabilization time (minimum 150us), SLOW_BIT can be cleared to 0. 1 : PLL is turned off. PLL is turned off only when SLOW_BIT is 1. Initial State 0 Reserved MPLL_OFF [6] [5] - 0 SLOW_BIT [4] 0 : FCLK = Mpll (MPLL output) 1: SLOW mode FCLK = input clock / (2 x SLOW_VAL) (SLOW_VAL > 0) FCLK = input clock (SLOW_VAL = 0) input clock = XTIpll or EXTCLK 0 Reserved SLOW_VAL [3] [2:0] - The divider value for the slow clock when SLOW_BIT is on. - 0x4 CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER Register CLKDIVN Address 0x4C000014 R/W R/W Description Clock divider control register Reset Value 0x00000000 CLKDIVN Reserved HDIVN PDIVN Bit [2] [1] [0] Description Special bus clock ratio for the chip verification. 0: HCLK has the clock same as the FCLK. 1: HCLK has the clock same as the FCLK/2. 0: PCLK has the clock same as the HCLK. 1: PCLK has the clock same as the HCLK/2. Initial State 0 0 0 7-22 S3C2410X DMA 8 DMA OVERVIEW The S3C2410X supports four-channel DMA controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the following four cases: 1) both source and destination are in the system bus, 2) the source is in the system bus while the destination is in the peripheral bus, 3) the source is in the peripheral bus while the destination is in the system bus, and 4) both source and destination are in the peripheral bus. The main advantage of the DMA is that it can transfer the data without CPU intervention. The operation of DMA can be initiated by software, or requests from internal peripherals or external request pins. 8-1 DMA S3C2410X DMA REQUEST SOURCES Each channel of the DMA controller can select one of DMA request source among four DMA sources if H/W DMA request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) Table 8-1 shows four DMA sources for each channel. Table 8-1. DMA Request Sources for Each Channel Source0 Ch-0 Ch-1 Ch-2 Ch-3 nXDREQ0 nXDREQ1 I2SSDO UART2 Source1 UART0 UART1 I2SSDI SDI Source2 SDI I2SSDI SDI SPI1 Source3 Timer SPI0 Timer Timer Source4 USB device EP1 USB device EP2 USB device EP3 USB device EP4 Here, nXDREQ0 and nXDREQ1 represent two external sources(External Devices), and I2SSDO and I2SSDI represent IIS transmitting and receiving, respectively. DMA OPERATION DMA uses three-state FSM (finite state machine) for its operation, which is described in the three following steps: State-1.As an initial state, the DMA waits for a DMA request. If it comes, it goes to state-2. At this state, DMA ACK and INT REQ are 0. State-2.In this state, DMA ACK becomes 1 and the counter (CURR_TC) is loaded from DCON[19:0] register. Note that the DMA ACK remains 1 until it is cleared later. State-3.In this state, sub-FSM handling the atomic operation of DMA is initiated. The sub-FSM reads the data from the source address and then writes it to destination address. In this operation, data size and transfer size (single or burst) are considered. This operation is repeated until the counter (CURR_TC) becomes 0 in Whole service mode, while performed only once in Single service mode. The main FSM (this FSM) counts down the CURR_TC when the sub-FSM finishes each of atomic operation. In addition, this main FSM asserts the INT REQ signal when CURR_TC becomes 0 and the interrupt setting of DCON[29] register is set to 1. In addition, it clears DMA ACK if one of the following conditions is met. 1) CURR_TC becomes 0 in the Whole service mode 2) Atomic operation finishes in the Single service mode. Note that in the Single service mode, these three states of main FSM are performed and then stops, and waits for another DMA REQ. And if DMA REQ comes in, all three states are repeated. Therefore, DMA ACK is asserted and then deasserted for each atomic transfer. In contrast, in the Whole service mode, main FSM waits at state-3 until CURR_TC becomes 0. Therefore, DMA ACK is asserted during all the transfers and then deasserted when TC reaches 0. However, INT REQ is asserted only if CURR_TC becomes 0 regardless of the service mode (Single service mode or Whole service mode). 8-2 S3C2410X DMA EXTERNAL DMA DREQ/DACK PROTOCOL There are three types of external DMA request/acknowledge protocols (Single service Demand, Single service Handshake and Whole service Handshake mode). Each type defines how the signals like DMA request and acknowledge are related to these protocols. Basic DMA Timing The DMA service means performing paired Reads and Writes cycles during DMA operation, which can make one DMA operation. Figure 8-1 shows the basic Timing in the DMA operation of the S3C2410X. -- The setup time and the delay time of XnXDREQ and XnXDACK are the same in all the modes. -- If the completion of XnXDREQ meets its setup time, it is synchronized twice and then XnXDACK is asserted. -- After assertion of XnXDACK, DMA requests the bus and if it gets the bus it performs its operations. XnXDACK is deasserted when DMA operation is completed. XSCLK tXRS XnXDREQ tXAD XnXDACK Min. 3SCLK tCADL Read Write tXRS tCADH Figure 8-1. Basic DMA Timing Diagram Table 8-2. DMA Controller Module Signal Timing Constants (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter eXternal Request Setup aCcess to Ack Delay when Low transition aCcess to Ack Delay when High transition eXternal Request Delay Symbol tXRS tCADL tCADH tXAD Min 2 9 9 2 Typ. - - - - Max 6 11 11 - Unit ns ns ns SCLK 8-3 DMA S3C2410X Demand/Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the differences between the two modes. At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ. Demand Mode -- If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be asserted. Handshake Mode -- If XnXDREQ is deasserted, DMA deasserts XnXDACK in 2cycles. Otherwise it waits until XnXDREQ is deasserted. CAUTION XnXDREQ has to be asserted (low) only after the deassertion (high) of XnXDACK. XSCLK Demand Mode XnXDREQ 2cycles 1st Transfer 2nd Transfer Read BUS Acquisiton ~ ~ Write ~ ~ XnXDACK Double synch Read Actual Transfer ~ ~ Write ~ ~ Handshake Mode XnXDREQ Read ~ ~ Write 2cycles Double synch 2cycles ~ ~ XnXDACK Figure 8-2. Demand/Handshake Mode Comparison 8-4 S3C2410X DMA Transfer Size -- There are two different transfer sizes; unit and Burst 4. -- DMA holds the bus firmly during the transfer of the chunk of data. Thus, other bus masters cannot get the bus. Burst 4 Transfer Size Four sequential Reads and Writes respectively are performed in the Burst 4 Transfer. NOTE: Unit Transfer size: One read and one write are performed. XSCLK ~ ~ XnXDREQ ~ ~ XnXDACK Double synch 3 cycles ~ ~ Read ~ ~ Read ~ ~ Read ~ ~ Read ~ ~ Write ~ ~ Write ~ ~ Write ~ ~ Write ~ ~ Figure 8-3. Burst 4 Transfer Size 8-5 DMA S3C2410X EXAMPLES Single service in Demand Mode with Unit Transfer Size The assertion of XnXDREQ is need for every unit transfer (Single service mode). The operation continues while the XnXDREQ is asserted (Demand mode), and one pair of Read and Write (Single transfer size) is performed. XSCLK XnXDREQ XnXDACK Double synch Read ~ ~ Write ~ ~ Read ~ ~ Write ~ ~ Figure 8-4. Single service in Demand Mode with Unit Transfer Size Single service in Handshake Mode with Unit Transfer Size XSCLK XnXDREQ XnXDACK Double synch Read ~ ~ Write ~ ~ 2 cycles Read ~ ~ Write ~ ~ Figure 8-5. Single service in Handshake Mode with Unit Transfer Size Whole service in Handshake Mode with Unit Transfer Size XSCLK XnXDREQ XnXDACK ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Double synch 3 cycles Read Write 2 cycles Read Write 2 cycles Read Write Figure 8-6. Whole service in Handshake Mode with Unit Transfer Size 8-6 S3C2410X DMA DMA SPECIAL REGISTERS Each DMA channel has nine control registers (36 in total since there are four channels for DMA controller). Six of the control registers control the DMA transfer, and other three ones monitor the status of DMA controller. The details of those registers are as follows. DMA INITIAL SOURCE (DISRC) REGISTER Register DISRC0 DISRC1 DISRC2 DISRC3 Address 0x4B000000 0x4B000040 0x4B000080 0x4B0000C0 R/W R/W R/W R/W R/W Description DMA 0 initial source register DMA 1 initial source register DMA 2 initial source register DMA 3 initial source register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DISRCn S_ADDR Bit [30:0] Description Base address (start address) of source data to transfer. This bit value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1. Initial State 0x00000000 DMA INITIAL SOURCE CONTROL (DISRCC) REGISTER Register DISRCC0 DISRCC1 DISRCC2 DISRCC3 Address 0x4B000004 0x4B000044 0x4B000084 0x4B0000C4 R/W R/W R/W R/W R/W Description DMA 0 initial source control register DMA 1 initial source control register DMA 2 initial source control register DMA 3 initial source control register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DISRCCn LOC Bit [1] Description Bit 1 is used to select the location of source. 0: the source is in the system bus (AHB). 1: the source is in the peripheral bus (APB). Initial State 0 INC [0] Bit 0 is used to select the address increment. 0 = Increment 1= Fixed If it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. If it is 1, the address is not changed after the transfer. (In the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer.) 0 8-7 DMA S3C2410X DMA INITIAL DESTINATION (DIDST) REGISTER Register DIDST0 DIDST1 DIDST2 DIDST3 Address 0x4B000008 0x4B000048 0x4B000088 0x4B0000B8 R/W R/W R/W R/W R/W Description DMA 0 initial destination register DMA 1 initial destination register DMA 2 initial destination register DMA 3 initial destination register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DIDSTn D_ADDR Bit [30:0] Description Base address (start address) of destination for the transfer. This bit value will be loaded into CURR_SRC only if the CURR_DST is 0 and the DMA ACK is 1. Initial State 0x00000000 DMA INITIAL DESTINATION CONTROL (DIDSTC) REGISTER Register DIDSTC0 DIDSTC1 DIDSTC2 DIDSTC3 Address 0x4B00000C 0x4B00004C 0x4B00008C 0x4B0000CC R/W R/W R/W R/W R/W Description DMA 0 initial destination control register DMA 1 initial destination control register DMA 2 initial destination control register DMA 3 initial destination control register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DIDSTCn LOC Bit [1] Description Bit 1 is used to select the location of destination. 0: the destination is in the system bus (AHB). 1: the destination is in the peripheral bus (APB). Initial State 0 INC [0] Bit 0 is used to select the address increment. 0 = Increment 1= Fixed If it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. If it is 1, the address is not changed after the transfer. (In the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer.) 0 8-8 S3C2410X DMA DMA CONTROL (DCON) REGISTER Register DCON0 DCON1 DCON2 DCON3 Address 0x4B000010 0x4B000050 0x4B000090 0x4B0000D0 R/W R/W R/W R/W R/W Description DMA 0 control register DMA 1 control register DMA 2 control register DMA 3 control register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DCONn DMD_HS Bit [31] Description Select one between Demand mode and Handshake mode. 0: Demand mode is selected. 1: Handshake mode is selected. In both modes, DMA controller starts its transfer and asserts DACK for a given asserted DREQ. The difference between the two modes is whether it waits for the deasserted DACK or not. In the Handshake mode, DMA controller waits for the deasserted DREQ before starting a new transfer. If it finds the deasserted DREQ, it deasserts DACK and waits for another asserted DREQ. In contrast, in the Demand mode, DMA controller does not wait until the DREQ is deasserted. It just deasserts DACK and then starts another transfer if DREQ is asserted. We recommend using Handshake mode for external DMA request sources to prevent unintended starts of new transfers. Initial State 0 SYNC [30] Select DREQ/DACK synchronization. 0: DREQ and DACK are synchronized to PCLK (APB clock). 1: DREQ and DACK are synchronized to HCLK (AHB clock). Therefore, for devices attached to AHB system bus, this bit has to be set to 1, while for those attached to APB system, it should be set to 0. For the devices attached to external systems, the user should select this bit depending on which the external system is synchronized with between AHB system and APB system. 0 INT [29] Enable/Disable the interrupt setting for CURR_TC (terminal count) 0: CURR_TC interrupt is disabled. The user has to view the transfer count in the status register (i.e. polling). 1: interrupt request is generated when all the transfer is done (i.e. CURR_TC becomes 0). 0 TSZ [28] Select the transfer size of an atomic transfer (i.e. transfer performed each time DMA owns the bus before releasing the bus). 0: a unit transfer is performed. 1: a burst transfer of length four is performed. 0 8-9 DMA S3C2410X DMA CONTROL (DCON) REGISTER (Continued) DCONn SERVMODE Bit [27] Description Select the service mode between Single service mode and Whole service mode. 0: Single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request. 1: Whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. In this mode, additional request are not required. Note that even in the Whole service mode, DMA releases the bus after each atomic transfer and then tries to re-get the bus to prevent starving of other bus masters. HWSRCSEL [26:24] Select DMA request source for each DMA. DCON0: 000:nXDREQ0 001:UART0 DCON1: 000:nXDREQ1 001:UART1 DCON2: 000:I2SSDO DCON3: 000:UART2 001:I2SSDI 001:SDI 010:SDI 011:Timer 100:USB device EP1 100:USB device EP2 100:USB device EP3 100:USB device EP4 010:I2SSDI 011:SPI 010:SDI 010:SPI 011:Timer 011:Timer Initial State 0 00 These bits control the 4-1 MUX to select the DMA request source of each DMA. These bits have meanings only if H/W request mode is selected by DCONn[23]. SWHW_SE L [23] Select the DMA source between software (S/W request mode) and hardware (H/W request mode). 0: S/W request mode is selected and DMA is triggered by setting SW_TRIG bit of DMASKTRIG control register. 1: DMA source selected by bit[26:24] triggers the DMA operation. RELOAD [22] Set the reload on/off option. 0: auto reload is performed when a current value of transfer count becomes 0 (i.e. all the required transfers are performed). 1: DMA channel (DMA REQ) is turned off when a current value of transfer count becomes 0. The channel on/off bit (DMASKTRIGn[1]) is set to 0 (DREQ off) to prevent unintended further start of new DMA operation. DSZ [21:20] Data size to be transferred. 00 = Byte 10 = Word TC [19:0] 01 = Half word 11 = reserved 00000 00 0 0 Initial transfer count (or transfer beat). Note that the actual number of bytes that are transferred is computed by the following equation: DSZ x TSZ x TC. Where, DSZ, TSZ (1 or 4), and TC represent data size (DCONn[21:20]), transfer size (DCONn[28]), and initial transfer count, respectively. This value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1. 8-10 S3C2410X DMA DMA STATUS (DSTAT) REGISTER Register DSTAT0 DSTAT1 DSTAT2 DSTAT3 Address 0x4B000014 0x4B000054 0x4B000094 0x4B0000D4 R/W R R R R Description DMA 0 count register DMA 1 count register DMA 2 count register DMA 3 count register Reset Value 000000h 000000h 000000h 000000h DSTATn STAT Bit [21:20] Description Status of this DMA controller. 00: Indicates that DMA controller is ready for another DMA request. 01: Indicates that DMA controller is busy for transfers. Initial State 00b CURR_TC [19:0] Current value of transfer count. Note that transfer count is initially set to the value of DCONn[19:0] register and decreased by one at the end of every atomic transfer. 00000h DMA CURRENT SOURCE (DCSRC) REGISTER Register DCSRC0 DCSRC1 DCSRC2 DCSRC3 Address 0x4B000018 0x4B000058 0x4B000098 0x4B0000D8 R/W R R R R Description DMA 0 current Source Register DMA 1 current Source Register DMA 2 current Source Register DMA 3 current Source Register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DCSRCn CURR_SRC Bit [30:0] Description Current source address for DMAn Initial State 0x00000000 8-11 DMA S3C2410X CURRENT DESTINATION (DCDST) REGISTER Register DCDST0 DCDST1 DCDST2 DCDST3 Address 0x4B00001C 0x4B00005C 0x4B00009C 0x4B0000DC R/W R R R R Description DMA 0 current destination register DMA 1 current destination register DMA 2 current destination register DMA 3 current destination register Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 DCDSTn CURR_DST Bit [30:0] Description Current destination address for DMAn Initial State 0x00000000 8-12 S3C2410X DMA DMA MASK TRIGGER (DMASKTRIG) REGISTER Register DMASKTRIG0 DMASKTRIG1 DMASKTRIG2 DMASKTRIG3 Address 0x4B000020 0x4B000060 0x4B0000A0 0x4B0000E0 R/W R/W R/W R/W R/W Description DMA 0 mask trigger register DMA 1 mask trigger register DMA 2 mask trigger register DMA 3 mask trigger register Reset Value 000 000 000 000 DMASKTRIGn STOP Bit [2] Stop the DMA operation. Description 1: DMA stops as soon as the current atomic transfer ends. If there is no current running atomic transfer, DMA stops immediately. The CURR_TC will be 0. NOTE: Due to possible current atomic transfer, "stop" operation may take several cycles. The finish of the operation (i.e. actual stop time) can be detected as soon as the channel on/off bit (DMASKTRIGn[1]) is set to off. This stop is "actual stop". Initial State 0 ON_OFF [1] DMA channel on/off bit. 0: DMA channel is turned off. (DMA request to this channel is ignored.) 1: DMA channel is turned on and the DMA request is handled. This bit is automatically set to off if we set the DCONn[22] bit to "no auto reload" and/or STOP bit of DMASKTRIGn to "stop". Note that when DCON[22] bit is "no auto reload", this bit becomes 0 when CURR_TC reaches 0. If the STOP bit is 1, this bit becomes 0 as soon as the current atomic transfer is completed. NOTE: This bit should not be changed manually during DMA operations (i.e. this has to be changed only by using DCON[22] or STOP bit). 0 SW_TRIG [0] Trigger the DMA channel in S/W request mode. 1: it requests a DMA operation to this controller. Note that this trigger gets effective after S/W request mode has to be selected (DCONn[23]) and channel ON_OFF bit has to be set to 1 (channel on). When DMA operation starts, this bit is cleared automatically. 0 NOTE: You can freely change the values of DISRC register, DIDST registers, and TC field of DCON register. Those changes take effect only after the finish of current transfer (i.e. when CURR_TC becomes 0). On the other hand, any change made to other registers and/or fields takes immediate effect. Therefore, be careful in changing those registers and fields. 8-13 DMA S3C2410X S/W Work-Around The DMA auto-reload is occurred only when the DMA request is issued after the DMA counter reaches 0. So, the following code should be used in the DMA done interrupt handler before setting the DMA source address, destination address and counter register for the next auto-reload. This code will wait until the first DMA request is issued and the previous auto-reload value is loaded. while((rDSTATn&0xfffff)==0); 8-14 S3C2410X I/O PORTS 9 I/O PORTS OVERVIEW The S3C2410X has 117 multi-functional input/output port pins. The ports are: -- Port A (GPA): 23-output port -- Port B (GPB): 11-input/output port -- Port C (GPC): 16-input/output port -- Port D (GPD): 16-input/output port -- Port E (GPE): 16-input/output port -- Port F (GPF): 8-input/output port -- Port G (GPG): 16-input/output port -- Port H (GPH): 11-input/output port Each port can be easily configured by software to meet various system configurations and design requirements. You have to define which function of each pin is used before starting the main program. If a pin is not used for multiplexed functions, the pin can be configured as I/O ports. Initial pin states are configured seamlessly to avoid problems. 9-1 I/O PORTS S3C2410X Table 9-1. S3C2410X Port Configuration (Sheet 1 of 5) Port A GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12 GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Output only Selectable Pin Functions nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9-2 S3C2410X I/O PORTS Table 9-1. S3C2410X Port Configuration (Sheet 2 of 5) Port B GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nXBREQ nXBACK TCLK0 TOUT3 TOUT2 TOUT1 TOUT0 - - - - - - - - - - - - - - - - - - - - - - Port C GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9-3 I/O PORTS S3C2410X Table 9-1. S3C2410X Port Configuration (Sheet 3 of 5) Port D GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 nSS0 nSS1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Port E GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4 GPE3 GPE2 GPE1 GPE0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions IICSDA IICSCL SPICLK0 SPIMOSI0 SPIMISO0 SDDAT3 SDDAT2 SDDAT1 SDDAT0 SDCMD SDCLK I2SSDO I2SSDI CDCLK I2SSCLK I2SLRCK - - - - - - - - - - - I2SSDI nSS0 - - - - - - - - - - - - - - - - - - - 9-4 S3C2410X I/O PORTS Table 9-1. S3C2410X Port Configuration (Sheet 4 of 5) Port F GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 - - - - - - - - - - Port G GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6 GPG5 GPG4 GPG3 GPG2 GPG1 GPG0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions EINT23 EINT22 EINT21 EINT20 EINT19 EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 nYPON YMON nXPON XMON TCLK1 - - - SPICLK1 SPIMOSI1 SPIMISO1 LCD_PWREN nSS1 nSS0 - - - - - - - - - - - - - - - - - - 9-5 I/O PORTS S3C2410X Table 9-1. S3C2410X Port Configuration (Sheet 5 of 5) Port H GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Selectable Pin Functions CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0 - - - nCTS1 nRTS1 - - - - - - - - - - - - - - - - - 9-6 S3C2410X I/O PORTS PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPACON-GPHCON) In the S3C2410X, most pins are multiplexed. So, It is require to determine which function is selected for each pin. port control register (PnCON) determines the function of each pin. If GPF0 - GPF7 and GPG0 - GPG7 are used for wakeup signals in Power-OFF mode, these ports must be configured in Interrupt mode. PORT DATA REGISTER (GPADAT-GPHDAT) If ports are configured as output ports, data can be written to the corresponding bit of the PnDAT. If ports are configured as input ports, the data can be read from the corresponding bit of the PnDAT. PORT PULL-UP REGISTER (GPBUP-GPHUP) The port pull-up register controls the pull-up resister enable/disable of each port group. When the corresponding bit is 0, the pull-up resister of the pin is enabled. When 1, the pull-up resister is disabled. If the port pull-up register is enabled, the pull-up resisters work without pin's functional setting (input, output, DATAn, EINTn, etc). MISCELLANEOUS CONTROL REGISTER This register controls DATA port pull-up resister, hi-z state, USB pad, and CLKOUT selection. EXTERNAL INTERRUPT CONTROL REGISTER (EXTINTN) The 24 external interrupts are requested by various signaling methods. The EXTINTn register configures the signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both edge trigger for the external interrupt request. The 8 external interrupt pin has a digital filter (refer to EINTFLTn on page 9-26). Only 16 EINT pins (EINT [15:0]) are used for wakeup sources. POWER_OFF MODE AND I/O PORTS All GPIO register values are preserved in Power_OFF mode. Refer to the Power_OFF mode in the chapter, Clock & Power Management. The EINTMASK can't prohibit the wake-up from Power_OFF mode, But, If ENTMASK is masking one of EINT[15:4], the wake-up can be done but the EINT4_7 bit and EINT8_23 bit of the SRCPND will not set to 1 just after the wake-up. 9-7 I/O PORTS S3C2410X I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS (GPACON/GPADAT) Register GPACON GPADAT Reserved Reserved Address 0x56000000 0x56000004 0x56000008 0x5600000C R/W R/W R/W - - Description Configure the pins of port A The data register for port A Reserved Reserved Reset Value 0x7FFFFF Undefined Undefined Undefined GPACON GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12 GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 Bit [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Output Description 1 = nFCE 0 = Output 1 = nRSTOUT (nRSTOUT = nRESET & nWDTRST & SW_RESET(MISCCR[16])) 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 0 = Output 1 = nFRE 1 = nFWE 1 = ALE 1 = CLE 1 = nGCS5 1 = nGCS4 1 = nGCS3 1 = nGCS2 1 = nGCS1 1 = ADDR26 1 = ADDR25 1 = ADDR24 1 = ADDR23 1 = ADDR22 1 = ADDR21 1 = ADDR20 1 = ADDR19 1 = ADDR18 1 = ADDR17 1 = ADDR16 1 = ADDR0 GPADAT GPA[22:0] Bit [22:0] Description When the port is configured as output port, the pin state is the same as the that of the corresponding bit. When the port is configured as functional pin, undefined value will be read. 9-8 S3C2410X I/O PORTS PORT B CONTROL REGISTERS (GPBCON, GPBDAT, and GPBUP) Register GPBCON GPBDAT GPBUP Reserved Address 0x56000010 0x56000014 0x56000018 0x5600001C R/W R/W R/W R/W - Description Configure the pins of port B The data register for port B Pull-up disable register for port B Reserved Reset Value 0x0 Undefined 0x0 Undefined GPBCON GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 Bit [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = nXDREQ0 00 = Input 10 = nXDACK0 00 = Input 10 = nXDREQ1 00 = Input 10 = nXDACK1 00 = Input 10 = nXBREQ 00 = Input 10 = nXBACK 00 = Input 10 = TCLK0 00 = Input 10 = TOUT3 00 = Input 10 = TOUT2 00 = Input 10 = TOUT1 00 = Input 10 = TOUT0 Description 01 = Output 11 = reserved 01 = Output 11 = reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = reserved 01 = Output 11 = reserved 01 = Output 11 = reserved 01 = Output 11 = reserved 01 = Output 11 = reserved] 01 = Output 11 = reserved 01 = Output 11 = reserved GPBDAT GPB[10:0] Bit [10:0] Description When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value will be read. GPBUP GPB[10:0] Bit [10:0] Description 0: The pull-up function attached to to the corresponding port pin is enabled. 1: The pull-up function is disabled. 9-9 I/O PORTS S3C2410X PORT C CONTROL REGISTERS (GPCCON, GPCDAT, and GPCUP) Register GPCCON GPCDAT GPCUP Reserved Address 0x56000020 0x56000024 0x56000028 0x5600002C R/W R/W R/W R/W - Description Configure the pins of port C The data register for port C Pull-up disable register for port C Reserved Reset Value 0x0 Undefined 0x0 Undefined GPCCON GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0 Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = VD[7] 00 = Input 10 = VD[6] 00 = Input 10 = VD[5] 00 = Input 10 = VD[4] 00 = Input 10 = VD[3] 00 = Input 10 = VD[2] 00 = Input 10 = VD[1] 00 = Input 10 = VD[0] 00 = Input 10 = LCDVF2 00 = Input 10 = LCDVF1 00 = Input 10 = LCDVF0 00 = Input 10 = VM 00 = Input 10 = VFRAME 00 = Input 10 = VLINE 00 = Input 10 = VCLK 00 = Input 10 = LEND Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved GPCDAT Bit Description 9-10 S3C2410X I/O PORTS GPC[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value will be read. GPCUP GPC[15:0] Bit [15:0] Description 0: The pull-up function attached to to the corresponding port pin is enabled. 1: The pull-up function is disabled. 9-11 I/O PORTS S3C2410X PORT D CONTROL REGISTERS (GPDCON, GPDDAT, and GPDUP) Register GPDCON GPDDAT GPDUP Reserved Address 0x56000030 0x56000034 0x56000038 0x5600003C R/W R/W R/W R/W - Description Configure the pins of port D The data register for port D Pull-up disable register for port D Reserved Reset Value 0x0 Undefined 0xF000 Undefined GPDCON GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0 Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = VD23 00 = Input 10 = VD22 00 = Input 10 = VD21 00 = Input 10 = VD20 00 = Input 10 = VD19 00 = Input 10 = VD18 00 = Input 10 = VD17 00 = Input 10 = VD16 00 = Input 10 = VD15 00 = Input 10 = VD14 00 = Input 10 = VD13 00 = Input 10 = VD12 00 = Input 10 = VD11 00 = Input 10 = VD10 00 = Input 10 = VD9 00 = Input 10 = VD8 Description 01 = Output 11 = nSS0 01 = Output 11 = nSS1 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved GPDDAT Bit Description 9-12 S3C2410X I/O PORTS GPD[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value will be read. GPDUP GPD[15:0] Bit [15:0] Description 0: The pull-up function attached to to the corresponding port pin is enabled. 1: The pull-up function is disabled. (GPD[15:12] are `pull-up disabled' state at the initial condition.) 9-13 I/O PORTS S3C2410X PORT E CONTROL REGISTERS (GPECON, GPEDAT, and GPEUP) Register GPECON GPEDAT GPEUP Reserved Address 0x56000040 0x56000044 0x56000048 0x5600004C R/W R/W R/W R/W - Description Configure the pins of port E The data register for port E pull-up disable register for port E Reserved Reset Value 0x0 Undefined 0x0 Undefined GPECON GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4 GPE3 GPE2 GPE1 GPE0 Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = IICSDA 00 = Input 10 = IICSCL 00 = Input 10 = SPICLK0 00 = Input 10 = SPIMOSI0 00 = Input 10 = SPIMISO0 00 = Input 10 = SDDAT3 00 = Input 10 = SDDAT2 00 = Input 10 = SDDAT1 00 = Input 10 = SDDAT0 00 = Input 10 = SDCMD 00 = Input 10 = SDCLK 00 = Input 10 = I2SSDO 00 = Input 10 = I2SSDI 00 = Input 10 = CDCLK 00 = Input 10 = I2SSCLK 00 = Input 10 = I2SLRCK Description 01 = Output (open drain output) 11 = Reserved 01 = Output (open drain output) 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = I2SSDI 01 = Output 11 = nSS0 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 9-14 S3C2410X I/O PORTS GPEDAT GPE[15:0] Bit [15:0] Description When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as a functional pin, undefined value will be read. GPEUP GPE[15:0] Bit [15:0] Description 0: The pull-up function attached to to the corresponding port pin is enabled. 1: The pull-up function is disabled. 9-15 I/O PORTS S3C2410X PORT F CONTROL REGISTERS (GPFCON, GPFDAT, and GPFPU) If GPF0 - GPF7 will be used for wakeup signals in Power-OFF mode, the ports will be set in Interrupt mode. Register GPFCON GPFDAT GPFUP Reserved Address 0x56000050 0x56000054 0x56000058 0x5600005C R/W R/W R/W R/W - Description Configure the pins of port F The data register for port F Pull-up disable register for port F Reserved Reset Value 0x0 Undefined 0x0 Undefined GPFCON GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 NOTES: Bit [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = EINT7 00 = Input 10 = EINT6 00 = Input 10 = EINT5 00 = Input 10 = EINT4 00 = Input 10 = EINT3 00 = Input 10 = EINT2 00 = Input 10 = EINT1 00 = Input 10 = EINT0 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved Description 1. GPFDAT GPF[7:0] Bit [7:0] Description When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value will be read. 2. GPFUP GPF[7:0] Bit [7:0] Description 0: The pull-up function attached to to the corresponding port pin is enabled. 1: The pull-up function is disabled. 9-16 S3C2410X I/O PORTS PORT G CONTROL REGISTERS (GPGCON, GPGDAT, AND GPGUP) If GPG[7:0] will be used for wakeup signals at Power-OFF mode, the ports will be set in Interrupt mode. Register GPGCON GPGDAT GPGUP Reserved Address 0x56000060 0x56000064 0x56000068 0x5600006C R/W R/W R/W R/W - Description Configure the pins of port G The data register for port G Pull-up disable register for port G Reserved Reset Value 0x0 Undefined 0xF800 Undefined GPGCON GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 (5V Tolerant Input) GPG9 (5V Tolerant Input) GPG8 (5V Tolerant Input) GPG7 GPG6 GPG5 GPG4 GPG3 GPG2 GPG1 GPG0 Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = EINT23 00 = Input 10 = EINT22 00 = Input 10 = EINT21 00 = Input 10 = EINT20 00 = Input 10 = EINT19 00 = Input 10 = EINT18 00 = Input 10 = EINT17 00 = Input 10 = EINT16 00 = Input 10 = EINT15 00 = Input 10 = EINT14 00 = Input 10 = EINT13 00 = Input 10 = EINT12 00 = Input 10 = EINT11 00 = Input 10 = EINT10 00 = Input 10 = EINT9 00 = Input 10 = EINT8 Description 01 = Output 11 = nYPON 01 = Output 11 = YMON 01 = Output 11 = nXPON 01 = Output 11 = XMON 01 = Output 11 = TCLK1 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = SPICLK1 01 = Output 11 = SPIMOSI1 01 = Output 11 = SPIMISO1 01 = Output 11 = LCD_PWREN 01 = Output 11 = nSS1 01 = Output 11 = nSS0 01 = Output 11 = Reserved 01 = Output 11 = Reserved 9-17 I/O PORTS S3C2410X GPGDAT GPG[15:0] Bit [15:0] Description When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value will be read. GPGUP GPG[15:0] Bit [15:0] Description 0: The pull-up function attached to to the corresponding port pin is enabled. 1: The pull-up function is disabled. (GPG[15:11] are `pull-up disabled' state at the initial condition.) 9-18 S3C2410X I/O PORTS PORT H CONTROL REGISTERS (GPHCON, GPHDAT, AND GPHUP) Register GPHCON GPHDAT GPHUP Reserved Address 0x56000070 0x56000074 0x56000078 0x5600007C R/W R/W R/W R/W - Description Configure the pins of port H The data register for port H Pull-up disable register for port H Reserved Reset Value 0x0 Undefined 0x0 Undefined GPHCON GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0 Bit [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 00 = Input 10 = CLKOUT1 00 = Input 10 = CLKOUT0 00 = Input 10 = UCLK 00 = Input 10 = RXD2 00 = Input 10 = TXD2 00 = Input 10 = RXD1 00 = Input 10 = TXD1 00 = Input 10 = RXD0 00 = Input 10 = TXD0 00 = Input 10 = nRTS0 00 = Input 10 = nCTS0 Description 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = nCTS1 01 = Output 11 = nRTS1 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved 01 = Output 11 = Reserved GPHDAT GPH[10:0] Bit [10:0] Description When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin. When the port is configured as functional pin, undefined value will be read. GPHUP GPH[10:0] Bit [10:0] Description 0: The pull-up function attached to to the corresponding port pin is enabled. 1: The pull-up function is disabled. 9-19 I/O PORTS S3C2410X MISCELLANEOUS CONTROL REGISTER (MISCCR) Pads related USB are controlled by this register for USB host, or for USB device. Register MISCCR Address 0x56000080 R/W R/W Description Miscellaneous control register Reset Value 0x10330 MISCCR Reserved nEN_SCKE nEN_SCLK1 nEN_SCLK0 nRSTCON Reserved USBSUSPND1 USBSUSPND0 Reserved CLKSEL1 Bit [21:20] [19] [18] [17] [16] [15:14] [13] [12] [11] [10:8] Reserved to 00b Description 0: SCKE = Normal 1: SCKE = L level Used to protect SDRAM during the Power_OFF moe. 0: SCLK1= SCLK 1: SCLK1= L level Used to protect SDRAM during the Power_OFF moe. 0: SCLK0= SCLK 1: SCLK0= L level Used to protect SDRAM during the Power_OFF moe. nRSTOUT software control(SW_RESET) 0: nRSTOUT = 0, 1: nRSTOUT = 1. Reserved to 00b [13] USB Port 1 mode 0 = Normal 1= Suspend [12] USB Port 0 mode 0 = Normal 1= Suspend Reserved to 0b CLKOUT1 output singnal source 000 = MPLL CLK 001 = UPLL CLK 011 = HCLK 100 = PCLK 11x = Reserved 0 CLKOUT0 output singnal source 000 = MPLL CLK 001 = UPLL CLK 011 = HCLK 100 = PCLK 11x = Reserved 010 = FCLK 101 = DCLK0 010 = FCLK 101 = DCLK1 Reserved CLKSEL0 [7] [6:4] USBPAD MEM_HZ_CON [3] [2] 0 = Use pads related USB for USB device 1 = Use pads related USB for USB host This bit is recommended to be 0. nGCS[7:0], nWE, nOE, nBE[3:0], nSRAS, nSCAS, ADDR[26:0] are affected during CLKCON[0] = 1. 0 = Hi-Z 1 = Previous state DATA[15:0] port pull-up resister 0 = Enabled 1 = Disabled DATA[31:16] port pull-up resister 0 = Enabled 1 = Disabled SPUCR_L SPUCR_H [1] [0] NOTE: CLKOUT is prepared only for monitoring an internal clock situation (On/Off status or frequency). 9-20 S3C2410X I/O PORTS DCLK CONTROL REGISTERS (DCLKCON) This register defines DCLKn signals, which work as clocks for external sources. See the following figure for how to make the DCLKn signals. The DCLKCON can actually operate only when CLKOUT[1:0] is set to send the DCLKn signals. Register DCLKCON Address 0x56000084 R/W R/W Description DCLK0/1 control register Reset Value 0x0 DCLKCON DCLK1CMP Bit [27:24] Description DCLK1 Compare value clock toggle value. ( < DCLK1DIV ) If the DCLK1DIV is n, Low level duration is ( n + 1 ). High level duration is ( (DCLK1DIV + 1) - ( n +1 ) ). DCLK1 Divide value DCLK1 frequency = source clock / ( DCLK1DIV + 1 ) 00b Select DCLK1 source clock 0 = PCLK 1 = UCLK ( USB ) DCLK1 Enable 0 = Disable 0000b DCLK0 Compare value clock toggle value. ( < DCLK0DIV ) If the DCLK0DIV is n, Low level duration is ( n + 1 ). High level duration is ( (DCLK0DIV + 1) - ( n +1 ) ). DCLK0 Divide value. DCLK0 frequency = source clock / ( DCLK0DIV + 1 ) 00b Select DCLK0 source clock 0 = PCLK 1 = UCLK ( USB ) DCLK0 Enable 0 = Disable 1 = Enable 1 = Enable DCLK1DIV Reserved DCLK1SelCK DCLK1EN Reserved DCLK0CMP [23:20] [19:18] [17] [16] [15:12] [11:8] DCLK0DIV Reserved DCLK0SelCK DCLK0EN [7:4] [3:2] [1] [0] DCLKnCMP + 1 DCLKnDIV + 1 9-21 I/O PORTS S3C2410X EXTERNAL INTERRUPT CONTROL REGISTER (EXTINTn) The 24 external interrupts can be requested by various signaling methods. The EXTINTn configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained at least for 40ns because of the noise filter (EINT[15:0]). Register EXTINT0 EXTINT1 EXTINT2 Address 0x56000088 0x5600008C 0x56000090 R/W R/W R/W R/W Description External interrupt control register 0 External interrupt control register 1 External interrupt control register 2 Reset Value 0x0 0x0 0x0 EXTINT0 EINT7 Bit [30:28] Description Set the signaling method of the EINT7. 000 = Low level 001 = High level 10x = Rising edge triggered Set the signaling method of the EINT6. 000 = Low level 001 = High level 10x = Rising edge triggered Set the signaling method of the EINT5. 000 = Low level 001 = High level 10x = Rising edge triggered Set the signaling method of the EINT4. 000 = Low level 001 = High level 10x = Rising edge triggered Set the signaling method of the EINT3. 000 = Low level 001 = High level 10x = Rising edge triggered Set the signaling method of the EINT2. 000 = Low level 001 = High level 10x = Rising edge triggered Set the signaling method of the EINT1. 000 = Low level 001 = High level 10x = Rising edge triggered Set the signaling method of the EINT0. 000 = Low level 001 = High level 10x = Rising edge triggered 01x = Falling edge triggered 11x = Both edge triggered 01x = Falling edge triggered 11x = Both edge triggered 01x = Falling edge triggered 11x = Both edge triggered 01x = Falling edge triggered 11x = Both edge triggered 01x = Falling edge triggered 11x = Both edge triggered 01x = Falling edge triggered 11x = Both edge triggered 01x = Falling edge triggered 11x = Both edge triggered 01x = Falling edge triggered 11x = Both edge triggered EINT6 [26:24] EINT5 [22:20] EINT4 [18:16] EINT3 [14:12] EINT2 [10:8] EINT1 [6:4] EINT0 [2:0] 9-22 S3C2410X I/O PORTS EXTINT1 Reserved EINT15 Bit [31] [30:28] Reserved Description Set the signaling method of the EINT15. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Set the signaling method of the EINT14. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Set the signaling method of the EINT13. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Set the signaling method of the EINT12. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Set the signaling method of the EINT11. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Set the signaling method of the EINT10. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Set the signaling method of the EINT9. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Set the signaling method of the EINT8. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved EINT14 [27] [26:24] Reserved EINT13 [23] [22:20] Reserved EINT12 [19] [18:16] Reserved EINT11 [15] [14:12] Reserved EINT10 [11] [10:8] Reserved EINT9 [7] [6:4] Reserved EINT8 [3] [2:0] 9-23 I/O PORTS S3C2410X EXTINT2 FLTEN23 EINT23 Bit [31] [30:28] Filter Enable for EINT23 Description 0 = Disable 1= Enable Set the signaling method of the EINT23. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT22 0 = Disable 1= Enable Set the signaling method of the EINT22. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT21 0 = Disable 1= Enable Set the signaling method of the EINT21. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT20 0 = Disable 1= Enable Set the signaling method of the EINT20. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT19 0 = Disable 1= Enable Set the signaling method of the EINT19. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT18 0 = Disable 1= Enable Set the signaling method of the EINT18. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT17 0 = Disable 1= Enable Set the signaling method of the EINT17. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Filter Enable for EINT16 0 = Disable 1= Enable Set the signaling method of the EINT16. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered FLTEN22 EINT22 [27] [26:24] FLTEN21 EINT21 [23] [22:20] FLTEN20 EINT20 [19] [18:16] FLTEN19 EINT19 [15] [14:12] FLTEN18 EINT18 [11] [10:8] FLTEN17 EINT17 [7] [6:4] FLTEN16 EINT16 [3] [2:0] 9-24 S3C2410X I/O PORTS EXTERNAL INTERRUPT FILTER REGISTER (EINTFLTn) The EINTFLTn controls the length of filter for 8 external interrupts (EINT[23:16]). Register EINTFLT0 EINTFLT1 EINTFLT2 EINTFLT3 Address 0x56000094 0x56000098 0x5600009C 0x4C6000A0 R/W R/W R/W R/W R/W Description Reserved Reserved External interrupt control register 2 External interrupt control register 3 0x0 0x0 Reset Value EINTFLT2 FLTCLK19 EINTFLT19 FLTCLK18 EINTFLT18 FLTCLK17 EINTFLT17 FLTCLK16 EINTFLT16 Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Filter clock of EINT19 0 = PCLK Filter width of EINT19 Filter clock of EINT18 0 = PCLK Filter width of EINT18 Filter clock of EINT17 0 = PCLK Filter width of EINT17 Filter clock of EINT16 0 = PCLK Filter width of EINT16 Description 1= EXTCLK/OSC_CLK (Selected by OM pin) 1= EXTCLK/OSC_CLK (Selected by OM pin) 1= EXTCLK/OSC_CLK (Selected by OM pin) 1= EXTCLK/OSC_CLK (Selected by OM pin) EINTFLT3 FLTCLK23 EINTFLT23 FLTCLK22 EINTFLT22 FLTCLK21 EINTFLT21 FLTCLK20 EINTFLT20 Bit [31] [30:24] [23] [22:16] [15] [14:8] [7] [6:0] Filter clock of EINT23 0 = PCLK Filter width of EINT23 Filter clock of EINT22 0 = PCLK Filter width of EINT22 Filter clock of EINT21 0 = PCLK Filter width of EINT21 Filter clock of EINT20 0 = PCLK Filter width of EINT20 Description 1= EXTCLK/OSC_CLK (Selected by OM pin) 1= EXTCLK/OSC_CLK (Selected by OM pin) 1= EXTCLK/OSC_CLK (Selected by OM pin) 1= EXTCLK/OSC_CLK (Selected by OM pin) 9-25 I/O PORTS S3C2410X EXTERNAL INTERRUPT MASK REGISTER (EINTMASK) Interrupt mask register for 20 external interrupts (EINT[23:4]). Register EINTMASK Address 0x560000A4 R/W R/W Description External interupt mask register Reset Value 0x00FFFFF0 EINTMASK EINT23 EINT22 EINT21 EINT20 EINT19 EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 Reserved Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3:0] 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 = Enable Interrupt 0 Description 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 1= Masked 9-26 S3C2410X I/O PORTS EXTERNAL INTERRUPT PENDING REGISTER (EINTPENDn) Interrupt pending register for 20 external interrupts (EINT[23:4]). You can clear a specific bit of the ENITPEND register by writing `1' on the corresponding bit of this register. Register EINTPEND Address 0x560000A8 R/W R/W Description External interupt pending register Reset Value 0x0 EINTPEND EINT23 EINT22 EINT21 EINT20 EINT19 EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 EINT4 Reserved Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3:0] 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 = Not requested 0 Description 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 1= Requested 9-27 I/O PORTS S3C2410X GENERAL STATUS REGISTER (GSTATUSn) Register GSTATUS0 GSTATUS1 GSTATUS2 GSTATUS3 GSTATUS4 Address 0x560000AC 0x560000B0 0x560000B4 0x560000B8 0x560000BC R/W R R R/W R/W R/W Description External pin status Chip ID Reset status Infrom register Infrom register Reset Value Undefined 0x32410000 0x1 0x0 0x0 GSTATUS0 nWAIT NCON RnB nBATT_FLT Bit [3] [2] [1] [0] Status of nWAIT pin Status of NCON pin Status of R/nB pin Status of nBATT_FLT pin Description GSTATUS1 CHIP ID Bit [31:0] ID register = 0x32410000 Description GSTATUS2 PWRST OFFRST WDTRST Bit [0] [1] [2] Description Power on reset, if this bit is set to "1". The setting is cleared by writing "1" to this bit. Power_OFF reset. The reset after the wakeup from Power_OFF mode. The setting is cleared by writing "1" to this bit. Watchdog reset. The reset derived from Watchdog timer. The setting is cleared by writing "1" to this bit. GSTATUS3 INFORM Bit [31:0] Description Inform register. This register is cleared by nRESET or watchdog timer. Otherwise, preserve data value. GSTATUS4 INFORM Bit [31:0] Description Inform register. This register is cleared by nRESET or watchdog timer. Otherwise, preserve data value. 9-28 S3C2410X PWM TIMER 10 OVERVIEW PWM TIMER The S3C2410X has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device. The timer 0 and 1 share an 8-bit prescaler, while the timer 2, 3 and 4 share other 8-bit prescaler. Each timer has a clock divider which 5 different divided signals (1/2, 1/4, 1/8, 1/16, and TCLK). Each timer block receives its own clock signals from the clock divider, which receives the clock from the corresponding 8-bit prescaler. The 8-bit prescaler is programmable and divides the PCLK according to the loading value, which is stored in TCFG0 and TCFG1 registers. The timer count buffer register (TCNTBn) has an initial value which is loaded into the down-counter when the timer is enabled. The timer compare buffer register (TCMPBn) has an initial value which is loaded into the compare register to be compared with the down-counter value. This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed. Each timer has its own 16-bit down counter, which is driven by the timer clock. When the down counter reaches zero, the timer interrupt request is generated to inform the CPU that the timer operation has been completed. When the timer counter reaches zero, the value of corresponding TCNTBn is automatically loaded into the down counter to continue the next operation. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn will not be reloaded into the counter. The value of TCMPBn is used for pulse width modulation (PWM). The timer control logic changes the output level when the down-counter value matches the value of the compare register in the timer control logic. Therefore, the compare register determines the turn-on time (or turn-off time) of an PWM output. FEATURE -- Five 16-bit timers -- Two 8-bit prescalers & Two 4-bit divider -- Programmable duty control of output waveform (PWM) -- Auto reload mode or one-shot pulse mode -- Dead-zone generator 10-1 PWM TIMER S3C2410X TCMPB0 TCNTB0 Dead Zone Generator Control Logic0 TOUT0 5:1 MUX Dead Zone PCLK 8-Bit Prescaler 1/2 1/4 1/8 1/16 TCLK0 Clock Divider TCMPB1 TCNTB1 TOUT1 5:1 MUX TCMPB2 5:1 MUX Control Logic1 Dead Zone TCNTB2 TOUT2 Control Logic2 1/2 1/4 8-Bit Prescaler 1/8 1/16 TCLK1 Clock Divider TCMPB3 TCNTB3 TOUT3 Control Logic3 Figure 10-1. 16-bit PWM Timer Block Diagram 5:1 MUX 5:1 MUX TCNTB4 Control Logic4 No Pin 10-2 S3C2410X PWM TIMER PWM TIMER OPERATION PRESCALER & DIVIDER An 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit divider settings 1/2 (PCLK = 50 MHz) 1/4 (PCLK = 50 MHz) 1/8 (PCLK = 50 MHz) 1/16 (PCLK = 50 MHz) Minimum resolution (prescaler = 0) 0.0400 us (25.0000 MHz) 0.0800 us (12.5000 MHz) 0.1600 us ( 6.2500 MHz) 0.3200 us ( 3.1250 MHz) Maximum resolution (prescaler = 255) 10.2400 us (97.6562 KHz) 20.4800 us (48.8281 KHz) 40.9601 us (24.4140 KHz) 81.9188 us (12.2070 KHz) Maximum interval (TCNTBn = 65535) 0.6710 sec 1.3421 sec 2.6843 sec 5.3686 sec BASIC TIMER OPERATION Start bit=1 Timer is started TCNTn=TCMPn Auto-reload TCNTn=TCMPn Timer is stopped TCMPn 1 0 TCNTn 3 3 2 1 0 2 1 0 0 TCNTBn=3 TCNTBn=1 Manual update=1 Auto-reload=1 TCNTBn=2 TCNTBn=0 Manual update=0 Auto-reload=1 Auto-reload Interrupt request Interrupt request TOUTn Command Status Figure 10-2. Timer Operations A timer (except the timer ch-5) has TCNTBn, TCNTn, TCMPBn and TCMPn. (TCNTn and TCMPn are the names of the internal registers. The TCNTn register can be read from the TCNTOn register) The TCNTBn and the TCMPBn are loaded into the TCNTn and the TCMPn when the timer reaches 0. When the TCNTn reaches 0, an interrupt request will occur if the interrupt is enabled. 10-3 PWM TIMER S3C2410X AUTO RELOAD & DOUBLE BUFFERING S3C2410X PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. The timer value can be written into Timer Count Buffer register (TCNTBn) and the current counter value of the timer can be read from Timer Count Observation register (TCNTOn). If the TCNTBn is read, the read value does not indicate the current state of the counter but the reload value for the next timer duration. The auto reload operation copies the TCNTBn into TCNTn when the TCNTn reaches 0. The value, written into the TCNTBn, is loaded to the TCNTn only when the TCNTn reaches 0 and auto reload is enabled. If the TCNTn becomes 0 and the auto reload bit is 0, the TCNTn does not operate any further. Write TCNTBn = 100 Start TCNTBn = 150 Write TCNTBn = 200 Auto-reload 150 100 100 200 Interrupt Figure 10-3. Example of Double Buffering Function 10-4 S3C2410X PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit. The following steps describe how to start a timer: 1) Write the initial value into TCNTBn and TCMPBn. 2) Set the manual update bit of the corresponding timer. It is recommended that you configure the inverter on/off bit. (whether use inverter or not). 3) Set start bit of the corresponding timer to start the timer (and clear the manual update bit). If the timer is stopped by force, the TCNTn retains the counter value and is not reloaded from TCNTBn. If a new value has to be set, perform manual update. NOTE Whenever TOUT inverter on/off bit is changed, the TOUTn logic value will also be changed whether the timer runs. Therefore, it is desirable that the inverter on/off bit is configured with the manual update bit. 10-5 PWM TIMER S3C2410X TIMER OPERATION 1 2 3 4 6 79 10 TOUTn 50 110 40 40 20 60 5 8 11 Figure 10-4. Example of a Timer Operation Figure 10-4 shows the result of the following procedure: 1. Enable the auto reload function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off). The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn, respectively. And then, set the TCNTBn and the TCMPBn to 80 (40+40) and 40, respectively, to determine the next reload value. 2. Set the start bit, provided that manual_update is 0 and the inverter is off and auto reload is on. The timer starts counting down after latency time within the timer resolution. 3. When the TCNTn has the same value as that of the TCMPn, the logic level of the TOUTn is changed from low to high. 4. When the TCNTn reaches 0, the interrupt request is generated and TCNTBn value is loaded into a temporary register. At the next timer tick, the TCNTn is reloaded with the temporary register value (TCNTBn). 5. In Interrupt Service Routine (ISR), the TCNTBn and the TCMPBn are set to 80 (20+60) and 60, respectively, for the next duration. 6. When the TCNTn has the same value as the TCMPn, the logic level of TOUTn is changed from low to high. 7. When the TCNTn reaches 0, the TCNTn is reloaded automatically with the TCNTBn, triggering an interrupt request. 8. In Interrupt Service Routine (ISR), auto reload and interrupt request are disabled to stop the timer. 9. When the value of the TCNTn is same as the TCMPn, the logic level of the TOUTn is changed from low to high. 10. Even when the TCNTn reaches 0, the TCNTn is not any more reloaded and the timer is stopped because auto reload has been disabled. 11. No more interrupt requests are generated. 10-6 S3C2410X PWM TIMER PULSE WIDTH MODULATION (PWM) 60 50 40 30 30 Write TCMPBn = 60 Write TCMPBn = 50 Write TCMPBn = 40 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value Figure 10-5. Example of PWM PWM function can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. Figure 10-5 shows a PWM value determined by TCMPBn. For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value. If an output inverter is enabled, the increment/decrement may be reversed. The double buffering function allows the TCMPBn, for the next PWM cycle, written at any point in the current PWM cycle by ISR or other routine. 10-7 PWM TIMER S3C2410X OUTPUT LEVEL CONTROL Inverter off Inverter on Initial State Period 1 Period 2 Timer Stop Figure 10-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1. Turn off the auto reload bit. And then, TOUTn goes to high level and the timer is stopped after the TCNTn reaches 0 (recommended). 2. Stop the timer by clearing the timer start/stop bit to 0. If TCNTn TCMPn, the output level is high. If TCNTn >TCMPn, the output level is low. 3. The TOUTn can be inverted by the inverter on/off bit in TCON. The inverter removes the additional circuit to adjust the output level. 10-8 S3C2410X PWM TIMER DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time. TOUT0 is the PWM output. nTOUT0 is the inversion of the TOUT0. If the dead zone is enabled, the output wave form of TOUT0 and nTOUT0 will be TOUT0_DZ and nTOUT0_DZ, respectively. nTOUT0_DZ is routed to the TOUT1 pin. In the dead zone interval, TOUT0_DZ and nTOUT0_DZ can never be turned on simultaneously. TOUT0 nTOUT0 Deadzone Interval TOUT0_DZ nTOUT0_DZ Figure 10-7. The Wave Form When a Dead Zone Feature is Enabled 10-9 PWM TIMER S3C2410X DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive. The timer, which generates the DMA request, is determined by setting DMA mode bits (in TCFG1 register). If one of timers is configured as DMA request mode, that timer does not generate an interrupt request. The others can generate interrupt normally. DMA mode configuration and DMA / interrupt operation DMA Mode 0000 0001 0010 0011 0100 0101 0110 DMA Request No select Timer0 Timer1 Timer2 Timer3 Timer4 No select Timer0 INT ON OFF ON ON ON ON ON Timer1 INT ON ON OFF ON ON ON ON Timer2 INT ON ON ON OFF ON ON ON Timer3 INT ON ON ON ON OFF ON ON Timer4 INT ON ON ON ON ON OFF ON PCLK INT4tmp DMAreq_en 101 nDMA_ACK nDMA_REQ INT4 Figure 10-8. Timer4 DMA Mode Operation 10-10 S3C2410X PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register TCFG0 Address 0x51000000 R/W R/W Description Configures the two 8-bit prescalers Reset Value 0x00000000 TCFG0 Reserved Dead zone length Prescaler 1 Prescaler 0 Bit [31:24] [23:16] [15:8] [7:0] Description These 8 bits determine the dead zone length. The 1 unit time of the dead zone length is equal to that of timer 0. These 8 bits determine prescaler value for Timer 2, 3 and 4. These 8 bits determine prescaler value for Timer 0 and 1. Initial State 0x00 0x00 0x00 0x00 10-11 PWM TIMER S3C2410X TIMER CONFIGURATION REGISTER1 (TCFG1) Register TCFG1 Address 0x51000004 R/W R/W Description 5-MUX & DMA mode selecton register Reset Value 0x00000000 TCFG1 Reserved DMA mode Bit [31:24] [23:20] Description Select DMA request channel 0000 = No select (all interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3 0101 = Timer4 0110 = Reserved Select MUX input for PWM Timer4. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer3. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer2. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK1 Select MUX input for PWM Timer1. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK0 Select MUX input for PWM Timer0. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = External TCLK0 Initial State 00000000 0000 MUX 4 [19:16] 0000 MUX 3 [15:12] 0000 MUX 2 [11:8] 0000 MUX 1 [7:4] 0000 MUX 0 [3:0] 0000 10-12 S3C2410X PWM TIMER TIMER CONTROL (TCON) REGISTER Register TCON Address 0x51000008 R/W R/W Description Timer control register Reset Value 0x00000000 TCON Timer 4 auto reload on/off Timer 4 manual update (note) Timer 4 start/stop Timer 3 auto reload on/off Timer 3 output inverter on/off Timer 3 manual update (note) Timer 3 start/stop Timer 2 auto reload on/off Timer 2 output inverter on/off Timer 2 manual update (note) Timer 2 start/stop Timer 1 auto reload on/off Timer 1 output inverter on/off Timer 1 manual update (note) Timer 1 start/stop Bit [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] Description Determine auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) Determine the manual update for Timer 4. 0 = No operation 1 = Update TCNTB4 Determine start/stop for Timer 4. 0 = Stop 1 = Start for Timer 4 Determine auto reload on/off for Timer 3. 0 = One-shot 1 = Interval mode (auto reload) Determine output inverter on/off for Timer 3. 0 = Inverter off 1 = Inverter on for TOUT3 Determine manual update for Timer 3. 0 = No operation 1 = Update TCNTB3 & TCMPB3 Determine start/stop for Timer 3. 0 = Stop 1 = Start for Timer 3 Determine auto reload on/off for Timer 2. 0 = One-shot 1 = Interval mode (auto reload) Determine output inverter on/off for Timer 2. 0 = Inverter off 1 = Inverter on for TOUT2 Determine the manual update for Timer 2. 0 = No operation 1 = Update TCNTB2 & TCMPB2 Determine start/stop for Timer 2. 0 = Stop 1 = Start for Timer 2 Determine the auto reload on/off for Timer1. 0 = One-shot 1 = Interval mode (auto reload) Determine the output inverter on/off for Timer1. 0 = Inverter off 1 = Inverter on for TOUT1 Determine the manual update for Timer 1. 0 = No operation 1 = Update TCNTB1 & TCMPB1 Determine start/stop for Timer 1. 0 = Stop 1 = Start for Timer 1 Initial state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTE: The bits have to be cleared at next writing. 10-13 PWM TIMER S3C2410X TIMER CONTROL (TCON) REGISTER (Continued) TCON Reserved Dead zone enable Timer 0 auto reload on/off Timer 0 output inverter on/off Timer 0 manual update (note) Timer 0 start/stop Bit [7:5] Reserved [4] [3] [2] [1] [0] Determine the dead zone operation. 0 = Disable 1 = Enable Determine auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) Determine the output inverter on/off for Timer 0. 0 = Inverter off 1 = Inverter on for TOUT0 Determine the manual update for Timer 0. 0 = No operation 1 = Update TCNTB0 & TCMPB0 Determine start/stop for Timer 0. 0 = Stop 1 = Start for Timer 0 0 0 0 0 0 Description Initial state NOTE: The bit have to be cleared at next writing. 10-14 S3C2410X PWM TIMER TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0/TCMPB0) Register TCNTB0 TCMPB0 Address 0x5100000C 0x51000010 R/W R/W R/W Description Timer 0 count buffer register Timer 0 compare buffer register Reset Value 0x00000000 0x00000000 TCMPB0 Timer 0 compare buffer register Bit [15:0] Description Set compare buffer value for Timer 0 Initial State 0x00000000 TCNTB0 Timer 0 count buffer register Bit [15:0] Description Set count buffer value for Timer 0 Initial State 0x00000000 TIMER 0 COUNT OBSERVATION REGISTER (TCNTO0) Register TCNTO0 Address 0x51000014 R/W R Description Timer 0 count observation register Reset Value 0x00000000 TCNTO0 Timer 0 observation register Bit [15:0] Description Set count observation value for Timer 0 Initial State 0x00000000 10-15 PWM TIMER S3C2410X TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Register TCNTB1 TCMPB1 Address 0x51000018 0x5100001C R/W R/W R/W Description Timer 1 count buffer register Timer 1 compare buffer register Reset Value 0x00000000 0x00000000 TCMPB1 Timer 1 compare buffer register Bit [15:0] Description Set compare buffer value for Timer 1 Initial State 0x00000000 TCNTB1 Timer 1 count buffer register Bit [15:0] Description Set count buffer value for Timer 1 Initial State 0x00000000 TIMER 1 COUNT OBSERVATION REGISTER (TCNTO1) Register TCNTO1 Address 0x51000020 R/W R Description Timer 1 count observation register Reset Value 0x00000000 TCNTO1 Timer 1 observation register Bit [15:0] Description Set count observation value for Timer 1 initial state 0x00000000 10-16 S3C2410X PWM TIMER TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2/TCMPB2) Register TCNTB2 TCMPB2 Address 0x51000024 0x51000028 R/W R/W R/W Description Timer 2 count buffer register Timer 2 compare buffer register Reset Value 0x00000000 0x00000000 TCMPB2 Timer 2 compare buffer register Bit [15:0] Description Set compare buffer value for Timer 2 Initial State 0x00000000 TCNTB2 Timer 2 count buffer register Bit [15:0] Description Set count buffer value for Timer 2 Initial State 0x00000000 TIMER 2 COUNT OBSERVATION REGISTER (TCNTO2) Register TCNTO2 Address 0x5100002C R/W R Description Timer 2 count observation register Reset Value 0x00000000 TCNTO2 Timer 2 observation register Bit [15:0] Description Set count observation value for Timer 2 Initial State 0x00000000 10-17 PWM TIMER S3C2410X TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Register TCNTB3 TCMPB3 Address 0x51000030 0x51000034 R/W R/W R/W Description Timer 3 count buffer register Timer 3 compare buffer register Reset Value 0x00000000 0x00000000 TCMPB3 Timer 3 compare buffer register Bit [15:0] Description Set compare buffer value for Timer 3 Initial State 0x00000000 TCNTB3 Timer 3 count buffer register Bit [15:0] Description Set count buffer value for Timer 3 Initial State 0x00000000 TIMER 3 COUNT OBSERVATION REGISTER (TCNTO3) Register TCNTO3 Address 0x51000038 R/W R Description Timer 3 count observation register Reset Value 0x00000000 TCNTO3 Timer 3 observation register Bit [15:0] Description Set count observation value for Timer 3 Initial State 0x00000000 10-18 S3C2410X PWM TIMER TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register TCNTB4 Address 0x5100003C R/W R/W Description Timer 4 count buffer register Reset Value 0x00000000 TCNTB4 Timer 4 count buffer register Bit [15:0] Description Set count buffer value for Timer 4 Initial State 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER (TCNTO4) Register TCNTO4 Address 0x51000040 R/W R Description Timer 4 count observation register Reset Value 0x00000000 TCNTO4 Timer 4 observation register Bit [15:0] Description Set count observation value for Timer 4 Initial State 0x00000000 10-19 PWM TIMER S3C2410X NOTES 10-20 S3C2410X UART 11 OVERVIEW UART The S3C2410X UART (Universal Asynchronous Receiver and Transmitter) provides three independent asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other words, the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART. The UART can support bit rates of up to 230.4K bps using system clock. If an external device provides the UART with UCLK, then the UART can operate at higher speed. Each UART channel contains two 16-byte FIFOs for receive and transmit. The S3C2410X UART includes programmable baud rates, infra-red (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. Each UART contains a baud-rate generator, a transmitter, a receiver and a control unit, as shown in Figure11-1. The baud-rate generator can be clocked by PCLK or UCLK. The transmitter and the receiver contain 16-byte FIFOs and data shifters. Data is written to FIFO and then copied to the transmit shifter before being transmitted. The data is then shifted out by the transmit data pin (TxDn). Meanwhile, received data is shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter. FEATURES -- RxD0, TxD0, RxD1, TxD1, RxD2, and TxD2 with DMA-based or interrupt-based operation -- UART Ch 0, 1, and 2 with IrDA 1.0 & 16-byte FIFO -- UART Ch 0 and 1 with nRTS0, nCTS0, nRTS1, and nCTS1 -- Supports handshake transmit/receive 11-1 UART S3C2410X BLOCK DIAGRAM Peripheral BUS Transmitter Transmit FIFO Register (FIFO mode) Transmit Buffer Register(16 Byte) Transmit Holding Register (Non-FIFO mode) Transmit Shifter TXDn Control Unit Receiver Buad-rate Generator Clock Source Receive Shifter RXDn Receive Buffer Register(16 Byte) Receive Holding Register (Non-FIFO mode only) Receive FIFO Register (FIFO mode) In FIFO mode, all 16 Byte of Buffer register are used as FIFO register. In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register. Figure 11-1. UART Block Diagram (with FIFO) 11-2 S3C2410X UART UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infra-red mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn). The transmitter can also produce the break condition, which forces the serial output to logic 0 state for one frame transmission time. This block transmits break signals after the present transmission word is transmitted completely. After the break signal transmission, it continuously transmits data into the Tx FIFO (Tx holding register in the case of Non-FIFO mode). Data Reception Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (ULCONn). The receiver can detect overrun error, parity error, frame error and break condition, each of which can set an error flag. -- The overrun error indicates that new data has overwritten the old data before the old data has been read. -- The parity error indicates that the receiver has detected an unexpected parity condition. -- The frame error indicates that the received data does not have a valid stop bit. -- The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one frame transmission time. Receive time-out condition occurs when it does not receive any data during the 3 word time (this interval follows the setting of Word Length bit) and the Rx FIFO is not empty in the FIFO mode. 11-3 UART S3C2410X Auto Flow Control (AFC) The S3C2410X's UART 0 and UART 1 support auto flow control with nRTS and nCTS signals. In case, it can be connected to external UARTs. If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. In AFC, nRTS depends on the condition of the receiver and nCTS signals control the operation of the transmitter. The UART's transmitter transfers the data in FIFO only when nCTS signals are activated (in AFC, nCTS means that other UART's FIFO is ready to receive data). Before the UART receives data, nRTS has to be activated when its receive FIFO has a spare more than 2-byte and has to be inactivated when its receive FIFO has a spare under 1-byte (in AFC, nRTS means that its own receive FIFO is ready to receive data). Transmission case in UART A Reception case in UART A UART A UART B UART A UART B TxD nCTS RxD nRTS RxD nRTS TxD nCTS Figure 11-2. UART AFC Interface NOTE: UART 2 does not support AFC function, because the S3C2410X has no nRTS2 and nCTS2. Example of Non Auto-Flow control (controlling nRTS and nCTS by software) Rx operation with FIFO 1. Select receive mode (Interrupt or DMA mode). 2. Check the value of Rx FIFO count in UFSTATn register. If the value is less than 15, users have to set the value of UMCONn[0] to '1' (activating nRTS), and if it is equal or larger than 15 users have to set the value to '0' (inactivating nRTS). 3. Repeat the Step 2. Tx operation with FIFO 1. Select transmit mode (Interrupt or DMA mode). 2. Check the value of UMSTATn[0]. If the value is '1' (activating nCTS), users write the data to Tx FIFO register. 11-4 S3C2410X UART RS-232C interface If users want to connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are needed. In this case, the users can control these signals with general I/O ports by software because the AFC does not support the RS-232C interface. Interrupt/DMA Request Generation Each UART of the S3C2410X has seven status (Tx/Rx/Error) signals: Overrun error, Parity error, Frame error, Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn). The overrun error, parity error, frame error and break condition are referred to as the receive error status, each of which can cause the receive error status interrupt request, if the receive-error-status-interrupt-enable bit is set to one in the control register, UCONn. When a receive-error-status-interrupt-request is detected, the signal causing the request can be identified by reading the value of UERSTSTn. When the receiver transfers the data of the receive shifter to the receive FIFO register in FIFO mode and the number of received data reaches Rx FIFO Trigger Level, Rx interrupt is generated, if Receive mode in control register (UCONn) is selected as 1 (Interrupt request or polling mode). In the Non-FIFO mode, transferring the data of the receive shifter to the receive holding register will cause Rx interrupt under the Interrupt request and polling mode. When the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level, Tx interrupt is generated, if Transmit mode in control register is selected as Interrupt request or polling mode. In the Non-FIFO mode, transferring data from the transmit holding register to the transmit shifter will cause Tx interrupt under the Interrupt request and polling mode. If the Receive mode and Transmit mode in control register are selected as the DMAn request mode then DMAn request occurs instead of Rx or Tx interrupt in the situation mentioned above. Table 11-1. Interrupts in Connection with FIFO Type Rx interrupt FIFO Mode Generated whenever receive data reaches the trigger level of receive FIFO. Generated when the number of data in FIFO does not reaches Rx FIFO trigger Level and does not receive any data during 3 word time (receive time out). This interval follows the setting of Word Length bit. Tx interrupt Generated whenever transmit data reaches the trigger level of transmit FIFO (Tx FIFO trigger Level). Generated when frame error, parity error, or break signal are detected. Generated when it gets to the top of the receive FIFO without reading out data in it (overrun error). Non-FIFO Mode Generated by the receive holding register whenever receive buffer becomes full. Generated by the transmit holding register whenever transmit buffer becomes empty. Generated by all errors. However if another error occurs at the same time, only one interrupt is generated. Error interrupt 11-5 UART S3C2410X UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out. To clear the error status FIFO, the URXHn with an error and UERSTATn must be read out. For example, It is assumed that the UART Rx FIFO receives A, B, C, D, and E characters sequentially and the frame error occurs while receiving 'B', and the parity error occurs while receiving 'D'. The actual UART receive error will not generate any error interrupt because the character, which was received with an error, has not been read yet. The error interrupt will occur when the character is read out. Figure 11-3 shows the UART receiving the five characters including the two errors. Time #0 #1 #2 #3 #4 #5 #6 Sequence Flow When no character is read out A, B, C, D, and E is received After A is read out After B is read out After C is read out After D is read out After E is read out Error Interrupt - - The frame error (in B) interrupt occurs. - The parity error (in D) interrupt occurs. - - The 'D' has to be read out. The 'B' has to be read out. Note RX-FIFO 'E' 'D' 'C' 'B' 'A' URXHn UERSTATn Error Status-FIFO Break Error Parity Error Frame Error Error Status Generator Unit Figure 11-3. UART Receiving 5 Characters with 2 Errors 11-6 S3C2410X UART Baud-Rate Generation Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the S3C2410X's internal system clock or UCLK. In other words, dividend is selectable by setting Clock Selection of UCONn. The baud-rate clock is generated by dividing the source clock (PCLK or UCLK) by 16 and a 16-bit divisor specified in the UART baud-rate divisor register (UBRDIVn). The UBRDIVn can be determined by the following expression: UBRDIVn = (int)(PCLK/(bps x 16) ) -1 Where, the divisor should be from 1 to (216-1). For accurate UART operation, the S3C2410X also supports UCLK as a dividend. If the S3C2410X uses UCLK, which is supplied by an external UART device or system, then the serial clock of UART is exactly synchronized with UCLK. So, the user can get the more precise UART operation. The UBRDIVn can be determined: UBRDIVn = (int)(UCLK / (bps x 16) ) -1 Where, the divisor should be from 1 to (216-1) and UCLK should be smaller than PCLK. For example, if the baud-rate is 115200 bps and PCLK or UCLK is 40 MHz, UBRDIVn is determined: UBRDIVn = (int)(40000000/(115200 x 16)) -1 = (int)(21.7) -1 = 21 -1 = 20 UART baud-rate generator error tolerance UART 10-bit time error should be less than 1.87%(3/160). tUPCLK = (UBRDIVn + 1) x 16 x 10 / PCLK tUEXACT = 10 / baud-rate tUPCLK : Real UART 10-bit time tUEXACT : Ideal UART 10-bit time UART error = (tUPCLK - tUEXACT) / tUEXACT x 100% Loopback Mode The S3C2410X UART provides a test mode referred to as the Loopback mode, to aid in isolating faults in the communication link. This mode structurally enables the connection of RXD and TXD in the UART. In this mode, therefore, transmitted data is received to the receiver, via RXD. This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel. This mode can be selected by setting the loopback bit in the UART control register (UCONn). Break Condition The break is defined as a continuous low level signal for one frame transmission time on the transmit data output. 11-7 UART S3C2410X Infra-Red (IR) Mode The S3C2410X UART block supports infra-red (IR) transmission and reception, which can be selected by setting the Infra-red-mode bit in the UART line control register (ULCONn). Figure 11-4 illustrates how to implement the IR mode. In IR transmit mode, the transmit pulse comes out at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero); In IR receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value (see the frame timing diagrams shown in Figure 11-6 and 11-7). TxD 0 TxD 1 IRS UART Block RxD 1 RE IrDA Tx Encoder IrDA Rx Decoder 0 RxD Figure 11-4. IrDA Function Block Diagram 11-8 S3C2410X UART SIO Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Figure 11-5. Serial I/O Frame Timing Diagram (Normal UART) IR Transmit Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Bit Time Pulse Width = 3/16 Bit Frame Figure 11-6. Infra-Red Transmit Mode Frame Timing Diagram IR Receive Frame Start Bit Data Bits Stop Bit 0 1 0 1 0 0 1 1 0 1 Figure 11-7. Infra-Red Receive Mode Frame Timing Diagram 11-9 UART S3C2410X UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control registers including ULCON0, ULCON1, and ULCON2 in the UART block. Register ULCON0 ULCON1 ULCON2 Address 0x50000000 0x50004000 0x50008000 R/W R/W R/W R/W Description UART channel 0 line control register UART channel 1 line control register UART channel 2 line control register Reset Value 0x00 0x00 0x00 ULCONn Reserved Infra-Red Mode Bit [7] [6] Description Determine whether or not to use the Infra-Red mode. 0 = Normal mode operation 1 = Infra-Red Tx/Rx mode Initial State 0 0 Parity Mode [5:3] Specify the type of parity generation and checking during UART transmit and receive operation. 0xx = No parity 100 = Odd parity 101 = Even parity 110 = Parity forced/checked as 1 111 = Parity forced/checked as 0 000 Number of Stop Bit [2] Specify how many stop bits are to be used for end-of-frame signal. 0 = One stop bit per frame 1 = Two stop bit per frame 0 Word Length [1:0] Indicate the number of data bits to be transmitted or received per frame. 00 = 5-bits 10 = 7-bits 01 = 6-bits 11 = 8-bits 00 11-10 S3C2410X UART UART CONTROL REGISTER There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block. Register UCON0 UCON1 UCON2 Address 0x50000004 0x50004004 0x50008004 R/W R/W R/W R/W Description UART channel 0 control register UART channel 1 control register UART channel 2 control register Reset Value 0x00 0x00 0x00 UCONn Clock Selection Bit Description 0=PCLK : UBRDIVn = (int)(PCLK / (bps x 16) ) -1 1=UCLK(@GPH8) : UBRDIVn = (int)(UCLK / (bps x 16) ) -1 Initial State 0 [10] Select PCLK or UCLK for the UART baud rate. Tx Interrupt Type [9] Interrupt request type. 0 = Pulse (Interrupt is requested as soon as the Tx buffer becomes empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.) 1 = Level (Interrupt is requested while Tx buffer is empty in Non-FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode.) 0 Rx Interrupt Type [8] Interrupt request type. 0 = Pulse (Interrupt is requested the instant Rx buffer receives the data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode.) 1 = Level (Interrupt is requested while Rx buffer is receiving data in Non-FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode.) 0 Rx Time Out Enable Rx Error Status Interrupt Enable [7] Enable/Disable Rx time out interrupt when UART FIFO is enabled. The interrupt is a receive interrupt. 0 = Disable 1 = Enable Enable the UART to generate an interrupt upon an exception, such as a break, frame error, parity error, or overrun error during a receive operation. 0 = Do not generate receive error status interrupt. 1 = Generate receive error status interrupt. 0 [6] 0 Loopback Mode [5] Setting loopback bit to 1 causes the UART to enter the loopback mode. This mode is provided for test purposes only. 0 = Normal operation 1 = Loopback mode Setting this bit causes the UART to send a break during 1 frame time. This bit is automatically cleared after sending the break signal. 0 = Normal transmit 1 = Send break signal 0 Send Break Signal [4] 0 11-11 UART S3C2410X UART CONTROL REGISTER (CONTINUED) Transmit Mode [3:2] Determine which function is currently able to write Tx data to the UART transmit buffer register. 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0), DMA3 request (Only for UART2) 11 = DMA1 request (Only for UART1) Receive Mode [1:0] Determine which function is currently able to read data from UART receive buffer register. 00 = Disable 01 = Interrupt request or polling mode 10 = DMA0 request (Only for UART0), DMA3 request (Only for UART2) 11 = DMA1 request (Only for UART1) NOTE: When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out the rest. 00 00 11-12 S3C2410X UART UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCON0, UFCON1 and UFCON2 in the UART block. Register UFCON0 UFCON1 UFCON2 Address 0x50000008 0x50004008 0x50008008 R/W R/W R/W R/W Description UART channel 0 FIFO control register UART channel 1 FIFO control register UART channel 2 FIFO control register Reset Value 0x0 0x0 0x0 UFCONn Tx FIFO Trigger Level Bit [7:6] Description Determine the trigger level of transmit FIFO. 00 = Empty 01 = 4-byte 10 = 8-byte 11 = 12-byte Determine the trigger level of receive FIFO. 00 = 4-byte 01 = 8-byte 10 = 12-byte 11 = 16-byte Auto-cleared after resetting FIFO 0 = Normal 1= Tx FIFO reset Auto-cleared after resetting FIFO 0 = Normal 1= Rx FIFO reset 0 = Disable 1 = Enable Initial State 00 Rx FIFO Trigger Level [5:4] 00 Reserved Tx FIFO Reset Rx FIFO Reset FIFO Enable [3] [2] [1] [0] 0 0 0 0 NOTE: When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the users should check the FIFO status and read out the rest. 11-13 UART S3C2410X UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCON0 and UMCON1 in the UART block. Register UMCON0 UMCON1 Reserved Address 0x5000000C 0x5000400C 0x5000800C R/W R/W R/W Description UART channel 0 Modem control register UART channel 1 Modem control register Reserved Reset Value 0x0 0x0 Undef UMCONn Reserved Auto Flow Control (AFC) Reserved Request to Send Bit [7:5] [4] [3:1] [0] These bits must be 0's 0 = Disable These bits must be 0's Description 1 = Enable Initial State 00 0 00 0 If AFC bit is enabled, this value will be ignored. In this case the S3C2410X will control nRTS automatically. If AFC bit is disabled, nRTS must be controlled by software. 0 = 'H' level (Inactivate nRTS) nRTS) 1 = 'L' level (Activate NOTE: UART 2 does not support AFC function, because the S3C2410X has no nRTS2 and nCTS2. 11-14 S3C2410X UART UART TX/RX STATUS REGISTER There are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1 and UTRSTAT2 in the UART block. Register UTRSTAT0 UTRSTAT1 UTRSTAT2 Address 0x50000010 0x50004010 0x50008010 R/W R R R Description UART channel 0 Tx/Rx status register UART channel 1 Tx/Rx status register UART channel 2 Tx/Rx status register Reset Value 0x6 0x6 0x6 UTRSTATn Transmitter empty Bit [2] Description Set to 1 automatically when the transmit buffer register has no valid data to transmit and the transmit shift register is empty. 0 = Not empty 1 = Transmitter (transmit buffer & shifter register) empty Set to 1 automatically when transmit buffer register is empty. 0 =The buffer register is not empty 1 = Empty (In Non-FIFO mode, Interrupt or DMA is requested. In FIFO mode, Interrupt or DMA is requested, when Tx FIFO Trigger Level is set to 00 (Empty)) If the UART uses the FIFO, users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit. Initial State 1 Transmit buffer empty [1] 1 Receive buffer data ready [0] Set to 1 automatically whenever receive buffer register contains valid data, received over the RXDn port. 0 = Empty 1 = The buffer register has a received data (In Non-FIFO mode, Interrupt or DMA is requested) If the UART uses the FIFO, users should check Rx FIFO Count bits and Rx FIFO Full bit in the UFSTAT register instead of this bit. 0 11-15 UART S3C2410X UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTAT0, UERSTAT1 and UERSTAT2 in the UART block. Register UERSTAT0 UERSTAT1 UERSTAT2 Address 0x50000014 0x50004014 0x50008014 R/W R R R Description UART channel 0 Rx error status register UART channel 1 Rx error status register UART channel 2 Rx error status register Reset Value 0x0 0x0 0x0 UERSTATn Reserved Frame Error Bit [3] [2] Description 0 = No frame error during receive 1 = Frame error (Interrupt is requested.) Set to 1 automatically whenever a frame error occurs during receive operation. 0 = No frame error during receive 1 = Frame error (Interrupt is requested.) 0 = No frame error during receive 1 = Frame error (Interrupt is requested.) Set to 1 automatically whenever an overrun error occurs during receive operation. 0 = No overrun error during receive 1 = Overrun error (Interrupt is requested.) Initial State 0 0 Reserved Overrun Error [1] [0] 0 0 NOTE: These bits (UERSATn[3:0]) are automatically cleared to 0 when the UART error status register is read. 11-16 S3C2410X UART UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTAT0, UFSTAT1 and UFSTAT2 in the UART block. Register UFSTAT0 UFSTAT1 UFSTAT2 Address 0x50000018 0x50004018 0x50008018 R/W R R R Description UART channel 0 FIFO status register UART channel 1 FIFO status register UART channel 2 FIFO status register Reset Value 0x00 0x00 0x00 UFSTATn Reserved Tx FIFO Full Bit [15:10] [9] Description Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 = 0-byte Tx FIFO data 15-byte 1 = Full Set to 1 automatically whenever receive FIFO is full during receive operation 0 = 0-byte Rx FIFO data 15-byte 1 = Full Number of data in Tx FIFO Number of data in Rx FIFO Initial State 0 0 Rx FIFO Full [8] 0 Tx FIFO Count Rx FIFO Count [7:4] [3:0] 0 0 11-17 UART S3C2410X UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTAT0 and UMSTAT1 in the UART block. Register UMSTAT0 UMSTAT1 Reserved Address 0x5000001C 0x5000401C 0x5000801C R/W R R - Description UART channel 0 Modem status register UART channel 1 Modem status register Reserved Reset Value 0x0 0x0 Undef UMSTAT0 Reserved Delta CTS Bit [3] [2] Description Indicate that the nCTS input to the S3C2410X has changed state since the last time it was read by CPU. (Refer to Figure 11-8.) 0 = Has not changed 1 = Has changed 0 = CTS signal is not activated (nCTS pin is high.) 1 = CTS signal is activated (nCTS pin is low.) Initial State 0 0 Reserved Clear to Send [1] [0] 0 0 nCTS Delta CTS Read_UMSTAT Figure 11-8. nCTS and Delta CTS Timing Diagram 11-18 S3C2410X UART UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three UART transmit buffer registers including UTXH0, UTXH1 and UTXH2 in the UART block. UTXHn has an 8-bit data for transmission data. Register UTXH0 UTXH1 UTXH2 Address 0x50000020(L) 0x50000023(B) 0x50004020(L) 0x50004023(B) 0x50008020(L) 0x50008023(B) R/W Description Reset Value - - - W UART channel 0 transmit buffer register (by byte) W UART channel 1 transmit buffer register (by byte) W UART channel 2 transmit buffer register (by byte) UTXHn TXDATAn Bit [7:0] Description Transmit data for UARTn Initial State - NOTE: (L): The endian mode is Little endian. (B): The endian mode is Big endian. UART RECEIVE BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three UART receive buffer registers including URXH0, URXH1 and URXH2 in the UART block. URXHn has an 8-bit data for received data. Register URXH0 URXH1 URXH2 Address 0x50000024(L) 0x50000027(B) 0x50004024(L) 0x50004027(B) 0x50008024(L) 0x50008027(B) R/W Description Reset Value - - - R UART channel 0 receive buffer register (by byte) R UART channel 1 receive buffer register (by byte) R UART channel 2 receive buffer register (by byte) URXHn RXDATAn Bit [7:0] Description Receive data for UARTn Initial State - NOTE: When an overrun error occurs, the URXHn must be read. If not, the next received data will also make an overrun error, even though the overrun bit of UERSTATn had been cleared. 11-19 UART S3C2410X UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block. The value stored in the baud rate divisor register (UBRDIVn), is used to determine the serial Tx/Rx clock rate (baud rate) as follows: UBRDIVn = (int)(PCLK / (bps x 16) ) -1 or UBRDIVn = (int)(UCLK / (bps x 16) ) -1 Where, the divisor should be from 1 to (216-1) and UCLK should be smaller than PCLK. For example, if the baud-rate is 115200 bps and PCLK or UCLK is 40 MHz, UBRDIVn is: UBRDIVn = (int)(40000000 / (115200 x 16) ) -1 = (int)(21.7) -1 = 21 -1 = 20 Register UBRDIV0 UBRDIV1 UBRDIV2 Address 0x50000028 0x50004028 0x50008028 R/W R/W R/W R/W Description Baud rate divisior register 0 Baud rate divisior register 1 Baud rate divisior register 2 Reset Value - - - UBRDIVn UBRDIV Bit [15:0] Description Baud rate division value UBRDIVn >0 Initial State - 11-20 S3C2410X BUS HOST CONTROLLER 12 OVERVIEW * * * * USB HOST CONTROLLER S3C2410X supports 2-port USB host interface as follows: OHCI Rev 1.0 compatible USB Rev1.1 compatible Two down stream ports Support for both LowSpeed and HighSpeed USB devices OHCI ROOT HUB REGS APP_SADR(8) APP_SDATA(32) HCI_DATA(32) CONTROL OHCI REGS CONTROL RCF0_RegData(32) CONTROL USB STATE CONTROL Cntl CONTROL TxEnl ROOT HUB & HOST SIE TxDpls TxDmns PORT S/M PORT S/M 1 X USB V R 2 X USB V R HCI SLAVE BLOCK APP_MDATA(32) HCI BUS HCM_ADR/ DATA(32) CONTROL HCI MASTER BLOCK LIST ED/TD_DATA(32) PROCESSOR BLOCK ED/TD STATUS(32) ED&TD REGS STATUS HC_DATA(8) DF_DATA(8) HCF_DATA(8) 64x8 FIFO Cntl Addr(6) FIFO_DATA(8) CTRL CTRL RcvData HSIE S/M RH_DATA(8) DF_DATA(8) DPLL RcvDpls RcvDmns ROOT HUB & HOST SIE PORT S/M EXT.FIFO STATUS 64x8 FIFO Figure 12-1. USB Host Controller Block Diagram 12-1 BUS HOST CONTROLLER S3C2410X USB HOST CONTROLLER SPECIAL REGISTERS The S3C2410X USB cost controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detail information. Table 12-1. OHCI Registers for USB Host Controller Register HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 Base Address 0x49000000 0x49000004 0x49000008 0x4900000C 0x49000010 0x49000014 0x49000018 0x4900001C 0x49000020 0x49000024 0x49000028 0x4900002C 0x49000030 0x49000034 0x49000038 0x4900003C 0x49000040 0x49000044 0x49000048 0x4900004C 0x49000050 0x49000054 0x49000058 R/W - - - - - - - - - - - - - - - - - - - - - - - Root hub group Frame counter group Memory pointer group Description Control and status group Reset Value - - - - - - - - - - - - - - - - - - - - - - - 12-2 S3C2410X USB DEVICE 13 OVERVIEW USB DEVICE CONTROLLER Universal Serial Bus (USB) device controller is designed to provide a high performance full speed function controller solution with DMA interface. USB device controller allows bulk transfer with DMA, interrupt transfer and control transfer. USB device controller supports: -- Full speed USB device controller compatible with the USB specification version 1.1 -- DMA interface for bulk transfer -- Five endpoints with FIFO EP0: 16byte (Register) EP1: 64byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP2: 64byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP3: 64byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA EP4: 64byte IN/OUT FIFO (dual port asynchronous RAM): interrupt or DMA -- Integrated USB Transceiver FEATURE -- Fully compliant with USB Specification Version 1.1 -- Full speed (12Mbps) device -- Integrated USB Transceiver -- Supports control, interrupt and bulk transfer -- Five endpoints with FIFO: One bi-directional control endpoint with 16-byte FIFO (EP0) Four bi-directional bulk endpoints with 64-byte FIFO (EP1, EP2, EP3, and EP4) -- Supports DMA interface for receive and transmit bulk endpoints. (EP1, EP2, EP3, and EP4) -- Independent 64byte receive and transmit FIFO to maximize throughput -- Supports suspend and remote wakeup function 13-1 USB DEVICE S3C2410X MC_ADDR[13:0] RT_VM_IN RT_VP_IN RXD RT_VP_OUT RT_VM_OUT RT_UX_OEN MC_DATA_IN[31:0] SIU MC_DATA_OUT[31:0] USB_CLK SYS_CLK SIE MCU & DMA I/F SYS_RESETN MC_WR WR_RDN MC_CSN GFI RT_UXSUSPEND MC_INTR DREQN[3:0] DACKN[3:0] FIFOs Figure 13-1. USB Device Controller Block Diagram 13-2 S3C2410X USB DEVICE USB DEVICE CONTROLLER SPECIAL REGISTERS This section describes detailed functionalities about register sets of USB device controller. All special function register is byte-accessible or word-accessible. If you access byte mode offset-address is different in little endian and big endian. All reserved bit is zero. Common indexed registers depend on INDEX register (INDEX_REG) (offset address: 0x178) value. For example if you want to write EP0 CSR register, you must write `0x00' on the INDEX_REG before writing IN_CSR1 register. NOTE All register must be resettled after performing Host Reset Signaling. Register Name NON INDEXED REGISTERS FUNC_ADDR_REG PWR_REG EP_INT_REG (EP0-EP4) USB_INT_REG USB_INT_EN_REG FRAME_NUM1_REG FRAME_NUM2_REG INDEX_REG EP0_FIFO_REG EP1_FIFO_REG EP2_FIFO_REG EP3_FIFO_REG EP4_FIFO_REG EP1_DMA_CON EP1_DMA_UNIT EP1_DMA_FIFO EP1_DMA_TTC_L EP1_DMA_TTC_M EP1_DMA_TTC_H EP2_DMA_CON EP2_DMA_UNIT EP2_DMA_FIFO EP2_DMA_TTC_L Function address register Power management register Endpoint interrupt register USB interrupt register USB Interrupt enable register Frame number 1 register Frame number 2 register Index register Endpoint0 FIFO register Endpoint1 FIFO register Endpoint2 FIFO register Endpoint3 FIFO register Endpoint4 FIFO register Endpoint1 DMA control register Endpoint1 DMA unit counter register Endpoint1 DMA FIFO counter register Endpoint1 DMA transfer counter low-byte register Endpoint1 DMA transfer counter middle-byte register Endpoint1 DMA transfer counter high-byte register Endpoint2 DMA control register Endpoint2 DMA unit counter register Endpoint2 DMA FIFO counter register Endpoint2 DMA transfer counter low-byte register 0x140(L) / 0x143(B) 0x144(L) / 0x147(B) 0x148(L) / 0x14B(B) 0x158(L) / 0x15B(B) 0x15C(L) / 0x15F(B) 0x16C(L) / 0x16F(B) 0x170(L) / 0x173(B) 0x174(L) / 0x177(B) 0x178(L) / 0x17B(B) 0x1C0(L) / 0x1C3(B) 0x1C4(L) / 0x1C7(B) 0x1C8(L) / 0x1CB(B) 0x1CC(L) / 0x1CF(B) 0x1D0(L) / 0x1D3(B) 0x200(L) / 0x203(B) 0x204(L) / 0x207(B) 0x208(L) / 0x20B(B) 0x20C(L) / 0x20F(B) 0x210(L) / 0x213(B) 0x214(L) / 0x217(B) 0x218(L) / 0x21B(B) 0x21C(L) / 0x21F(B) 0x220(L) / 0x223(B) 0x224(L) / 0x227(B) Description Offset Address EP_INT_EN_REG (EP0-EP4) Endpoint interrupt enable register 13-3 USB DEVICE S3C2410X USB Device Controller Special Registers (Continued) Register Name EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_CON EP3_DMA_UNIT EP3_DMA_FIFO EP3_DMA_TTC_L EP3_DMA_TTC_M EP3_DMA_TTC_H EP4_DMA_CON EP4_DMA_UNIT EP4_DMA_FIFO EP4_DMA_TTC_L EP4_DMA_TTC_M EP4_DMA_TTC_H MAXP_REG IN INDEXED REGISTERS IN_CSR1_REG/EP0_CSR IN_CSR2_REG OUT INDEXED REGISTERS OUT_CSR1_REG OUT_CSR2_REG OUT_FIFO_CNT1_REG OUT_FIFO_CNT2_REG EP out control status register 1 EP out control status register 2 EP out write count register 1 EP out write count register 2 0x190(L) / 0x193(B) 0x194(L) / 0x197(B) 0x198(L) / 0x19B(B) 0x19C(L) / 0x19F(B) EP In control status register 1/EP0 control status register EP In control status register 2 0x184(L) / 0x187(B) 0x188(L) / 0x18B(B) Description Endpoint2 DMA transfer counter middle-byte register Endpoint2 DMA transfer counter high-byte register Endpoint3 DMA control register Endpoint3 DMA unit counter register Endpoint3 DMA FIFO counter register Endpoint3 DMA transfer counter low-byte register Endpoint3 DMA transfer counter middle-byte register Endpoint3 DMA transfer counter high-byte register Endpoint4 DMA control register Endpoint4 DMA unit counter register Endpoint4 DMA FIFO counter register Endpoint4 DMA transfer counter low-byte register Endpoint4 DMA transfer counter middle-byte register Endpoint4 DMA transfer counter high-byte register Endpoint MAX packet register Offset Address 0x228(L) / 0x22B(B) 0x22C(L) / 0x22F(B) 0x240(L) / 0x243(B) 0x244(L) / 0x247(B) 0x248(L) / 0x24B(B) 0x24C(L) / 0x24F(B) 0x250(L) / 0x253(B) 0x254(L) / 0x247(B) 0x258(L) / 0x25B(B) 0x25C(L) / 0x25F(B) 0x260(L) / 0x263(B) 0x264(L) / 0x267(B) 0x268(L) / 0x26B(B) 0x26C(L) / 0x26F(B) 0x18C(L) / 0x18F(B) COMMON INDEXED REGISTERS 13-4 S3C2410X USB DEVICE FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG) This register maintains the USB device controller address assigned by the host. The Micro Controller Unit (MCU) writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token. Register FUNC_ADDR_REG Address 0x52000140(L) 0x52000143(B) R/W R/W (byte) Description Function address register Reset Value 0x00 FUNC_ADDR_REG ADDR_UPDATE Bit [7] MCU R /SET USB Description Initial State 0 R Set by the MCU whenever it updates the /CLEAR FUNCTION_ADDR field in this register. This bit will be cleared by USB when DATA_END bit in EP0_CSR register. R The MCU write the unique address, assigned by host, to this field. FUNCTION_ADDR [6:0] R/W 00 13-5 USB DEVICE S3C2410X POWER MANAGEMENT REGISTER (PWR_REG) This register acts as a power control register in the USB block. Register PWR_REG Address 0x52000144(L) 0x52000147(B) R/W R/W (byte) Description Power management register Reset Value 0x00 PWR_ADDR ISO_UPDATE Bit [7] MCU R/W USB R Description Used for ISO mode only. If set, GFI waits for a SOF token to set IN_PKT_RDY even though a packet to send is already loaded by MCU. If an IN token is received before a SOF token, then a zero length data packet will be sent. - Set by the USB if reset signaling is received from the host. This bit remains set as long as reset signaling persists on the bus Initial State 0 Reserved USB_RESET [6:4] [3] - R - SET - 0 MCU_RESUME [2] R/W R Set by the MCU for MCU Resume. /CLEAR The USB generates the resume signaling during 10ms, if this bit is set in suspend mode. SET Set by USB automatically when the device /CLEAR enter into suspend mode. It is cleared under the following conditions: 1) The MCU clears the MCU_RESUME bit by writing `0', in order to end remote resume signaling. 2) The resume signal form host is received. R Suspend mode enable control bit 0 = Disable (default). The device will not enter suspend mode. 1 = Enable suspend mode. 0 SUSPEND_MODE [1] R SUSPEND_EN [0] R/W 0 13-6 S3C2410X USB DEVICE INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) The USB core has two interrupt registers. These registers act as status registers for the MCU when it is interrupted. The bits are cleared by writing a `1' (not `0') to each bit that was set. Once the MCU is interrupted, MCU should read the contents of interrupt-related registers and write back to clear the contents if it is necessary. Register EP_INT_REG Address 0x52000148(L) 0x5200014B(B) R/W R/W (byte) Description EP interrupt pending/clear register Reset Value 0x00 EP_INT_REG EP1~EP4 Interrupt Bit [4:1] MCU R /CLEAR USB SET Description For BULK/INTERRUPT IN endpoints: Set by the USB under the following conditions: 1. IN_PKT_RDY bit is cleared. 2. FIFO is flushed 3. SENT_STALL set. For BULK/INTERRUPT OUT endpoints: Set by the USB under the following conditions: 1. Sets OUT_PKT_RDY bit 2. Sets SENT_STALL bit For ISO IN endpoints: Set by the USB under the following conditions: 1. UNDER_RUN bit is set 2. IN_PKT_RDY bit is cleared. 3. FIFO is flushed NOTE: Conditions 1 and 2 are mutually exclusive Initial State 0 For ISO OUT endpoints: Set by the USB under the following conditions: 1. OUT_PKT_RDY bit is set 2. OVER RUN bit is set. NOTE: Conditions 1 and 2 are mutually exclusive. EP0 Interrupt [0] R /CLEAR SET Correspond to endpoint 0 interrupt. Set by the USB under the following conditions: 1. OUT_PKT_RDY bit is set. 2. IN_PKT_RDY bit is cleared. 3. SENT_STALL bit is set 4. SETUP_END bit is set 5. DATA_END bit is cleared (it indicates the end of control transfer). 0 13-7 USB DEVICE S3C2410X Interrupt Register (EP_INT_REG/USB_INT_REG) (Continued) Register USB_INT_REG Address 0x52000158(L) 0x5200015B(B) R/W R/W (byte) Description USB interrupt pending/clear register Reset Value 0x00 USB_INT_REG RESET Interrupt RESUME Interrupt Bit [2] [1] MCU R /CLEAR R /CLEAR USB SET SET Description Set by the USB when it receives reset signaling. Set by the USB when it receives resume signaling, while in Suspend mode. If the resume occurs due to a USB reset, then the MCU is first interrupted with a RESUME interrupt. Once the clocks resume and the SE0 condition persists for 3ms, USB RESET interrupt will be asserted. Set by the USB when it receives suspend signalizing. This bit is set whenever there is no activity for 3ms on the bus. Thus, if the MCU does not stop the clock after the first suspend interrupt, it will continue to be interrupted every 3ms as long as there is no activity on the USB bus. By default, this interrupt is disabled. Initial State 0 0 SUSPEND Interrupt [0] R /CLEAR SET 0 NOTE: If the RESET interrupt is occurred, all USB device registers should be re-configured. 13-8 S3C2410X USB DEVICE INTERRUPT ENABLE REGISTER (EP_INT_EN_REG/USB_INT_REG) Corresponding to each interrupt register, The USB device controller also has two interrupt enable registers (except resume interrupt enable). By default, usb reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled. Register EP_INT_EN_REG Address 0x5200015C(L) 0x5200015F(B) R/W R/W (byte) Description Determine which interrupt is enabled Reset Value 0xFF EP_INT_EN_REG EP4_INT_EN EP3_INT_EN EP2_INT_EN EP1_INT_EN EP0_INT_EN Bit [4] [3] [2] [1] [0] MCU R/W R/W R/W R/W R/W USB R R R R R Description EP4 Interrupt Enable bit 0 = Interrupt disable EP3 Interrupt Enable bit 0 = Interrupt disable EP2 Interrupt Enable bit 0 = Interrupt disable EP1 Interrupt Enable bit 0 = Interrupt disable EP0 Interrupt Enable bit 0 = Interrupt disable 1 = Enable Initial State 1 1 1 = Enable 1 1 = Enable 1 1 = Enable 1 1 = Enable Register USB_INT_EN_REG Address 0x5200016C(L) 0x5200016F(B) R/W R/W (byte) Description Determine which interrupt is enabled Reset Value 0x04 INT_MASK_REG RESET_INT_EN Reserved SUSPEND_INT_EN Bit [2] [1] [0] MCU R/W - R/W USB R - R Description Reset interrupt enable bit 0 = Interrupt disable 1 = Enable - Suspend interrupt enable bit 0 = Interrupt disable 1 = Enable Initial State 1 0 0 13-9 USB DEVICE S3C2410X FRAME NUMBER REGISTER (FPAME_NUM1_REG/FRAME_NUM2_REG) When the host transfers USB packets, each Start Of Frame (SOF) packet includes a frame number. The USB device controller catches this frame number and loads it into this register automatically. Register FRAME_NUM1_REG Address 0x52000170(L) 0x52000173(B) R/W R (byte) Description Frame number lower byte register Reset Value 0x00 FRAME_NUM_REG FRAME_NUM1 Bit [7:0] MCU R USB W Description Frame number lower byte value Initial State 00 Register FRAME_NUM2_REG Address 0x52000174(L) 0x52000177(B) R/W R (byte) Description Frame number higher byte register Reset Value 0x00 FRAME_NUM_REG FRAME_NUM2 Bit [7:0] MCU R USB W Description Frame number higher byte value Initial State 00 13-10 S3C2410X USB DEVICE INDEX REGISTER (INDEX_REG) The INDEX register is used to indicate certain endpoint registers effectively. The MCU can access the endpoint registers (MAXP_REG, IN_CSR1_REG, IN_CSR2_REG, OUT_CSR1_REG, OUT_CSR2_REG, OUT_FIFO_CNT1_REG, and OUT_FIFO_CNT2_REG) for an endpoint inside the core using the INDEX register. Register INDEX_REG Address 0x52000178(L) 0x5200017B(B) R/W R/W (byte) Description Register index register Reset Value 0x00 INDEX_REG INDEX Bit [7:0] MCU R/W USB R Description Indicate a certain endpoint Initial State 00 13-11 USB DEVICE S3C2410X END POINT0 CONTROL STATUS REGISTER (EP0_CSR) This register has the control and status bits for Endpoint 0. Since a control transaction is involved with both IN and OUT tokens, there is only one CSR register, mapped to the IN CSR1 register. (share IN1_CSR and can access by writing index register "0" and read/write IN1_CSR) Register EP0_CSR Address 0x52000184(L) 0x52000187(B) R/W R/W (byte) Description Endpoint 0 status register Reset Value 0x00 EP0_CSR SERVICED_SETUP_ END SERVICED_OUT_ PKT_RDY SEND_STALL Bit [7] [6] [5] MCU W W R/W USB CLEAR CLEAR CLEAR Description The MCU should write a "1" to this bit to clear SETUP_END. The MCU should write a "1" to this bit to clear OUT_PKT_RDY. MCU should write a "1" to this bit at the same time it clears OUT_PKT_RDY, if it decodes an invalid token. 0 = Finish the STALL condition 1 = The USB issues a STALL and shake to the current control transfer. Set by the USB when a control transfer ends before DATA_END is set. When the USB sets this bit, an interrupt is generated to the MCU. When such a condition occurs, the USB flushes the FIFO and invalidates MCU access to the FIFO. Set by the MCU on the conditions below: 1. After loading the last packet of data into the FIFO, at the same time IN_PKT_RDY is set. 2. While it clears OUT_PKT_RDY after unloading the last packet of data. 3. For a zero length data phase. Set by the USB if a control transaction is stopped due to a protocol violation. An interrupt is generated when this bit is set. The MCU should write "0" to clear this bit. Initial State 0 0 0 SETUP_END [4] R SET 0 DATA_END [3] SET CLEAR 0 SENT_STALL [2] CLEAR SET 0 13-12 S3C2410X USB DEVICE END Point0 Control Status Register (EP0_CSR) (Continued) EP0_CSR IN_PKT_RDY Bit [1] MCU SET USB CLEAR Description Set by the MCU after writing a packet of data into EP0 FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB clears this bit, so as the MCU to load the next packet. For a zero length data phase, the MCU sets DATA_END at the same time. Set by the USB once a valid token is written to the FIFO. An interrupt is generated when the USB sets this bit. The MCU clears this bit by writing a "1" to the SERVICED_OUT_PKT_RDY bit. Initial State 0 OUT_PKT_RDY [0] R SET 0 13-13 USB DEVICE S3C2410X END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register IN_CSR1_REG Address 0x52000184(L) 0x52000187(B) R/W R/W (byte) Description IN END POINT control status register1 Reset Value 0x00 IN_CSR1_REG Reserved CLR_DATA_ TOGGLE Bit [7] [6] MCU - R/W USB - R/ CLEAR Description - Used in Set-up procedure. 0: There are alternation of DATA0 and DATA1 1: The data toggle bit is cleared and PID in packet will maintain DATA0 Set by the USB when an IN token issues a STALL handshake, after the MCU sets SEND_STALL bit to start STALL handshaking. When the USB issues a STALL handshake, IN_PKT_RDY is cleared 0: The MCU clears this bit to finish the STALL condition. 1: The MCU issues a STALL handshake to the USB. Set by the MCU if it intends to flush the packet in Input-related FIFO. This bit is cleared by the USB when the FIFO is flushed. The MCU is interrupted when this happens. If a token is in process, the USB waits until the transmission is complete before FIFO flushing. If two packets are loaded into the FIFO, only first packet (The packet is intended to be sent to the host) is flushed, and the corresponding IN_PKT_RDY bit is cleared Valid only For Iso mode. Set by the USB when in ISO mode, an IN token is received and the IN_PKT_RDY bit is not set. The USB sends a zero length data packet for such conditions, and the next packet that is loaded into the FIFO is flushed. This bit is cleared by writing 0. - Initial State 0 0 SENT_STALL [5] R/ CLEAR SET 0 SEND_STALL [4] W/R R 0 FIFO_FLUSH [3] R/W CLEAR 0 UNDER_RUN [2] R/ CLEAR Set 0 Reserved [1] - - 0 13-14 S3C2410X USB DEVICE END Point in Control Status Register (IN_CSR1_REG/IN_CSR2_REG) (Continued) IN_CSR1_REG IN_PKT_RDY Bit [0] MCU R/SET USB CLEAR Description Set by the MCU after writing a packet of data into the FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB clears this bit, so the MCU can load the next packet. While this bit is set, the MCU will not be able to write to the FIFO. If the MCU sets SEND STALL bit, this bit cannot be set. Initial State 0 Register IN_CSR2_REG Address 0x52000188(L) 0x5200018B(B) R/W R/W (byte) Description IN END POINT control status register2 Reset Value 0x20 IN_CSR2_REG AUTO_SET Bit [7] MCU R/W USB R Description If set, whenever the MCU writes MAXP data, IN_PKT_RDY will automatically be set by the core without any intervention from MCU. If the MCU writes less than MAXP data, IN_PKT_RDY bit has to be set by the MCU. Used only for endpoints whose transfer type is programmable. 1: Reserved 0: Configures endpoint to Bulk mode Used only for endpoints whose direction is programmable. 1: Configures Endpoint Direction as IN 0: Configures Endpoint Direction as OUT Determine whether the interrupt should be issued or not, when the EP1 IN_PKT_RDY condition happens. This is only useful for DMA mode. 0 = Interrupt enable, 1 = Interrupt Disable - Initial State 0 ISO [6] R/W R 0 MODE_IN [5] R/W R 1 IN_DMA_INT_EN [4] R/W R 0 Reserved [3:0] - - - 13-15 USB DEVICE S3C2410X END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) Register OUT_CSR1_REG Address 0x52000190(L) 0x52000193(B) R/W R/W (byte) Description End Point out control status register1 Reset Value 0x00 OUT_CSR1_REG CLR_DATA_ TOGGLE SENT_STALL Bit [7] [6] MCU R/W R/ CLEAR USB CLEAR SET Description When the MCU writes a 1 to this bit, the data toggle sequence bit is reset to DATA0. Set by the USB when an OUT token is ended with a STALL handshake. The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT TOKEN. 0: The MCU clears this bit to end the STALL condition handshake, IN PKT RDY is cleared. 1: The MCU issues a STALL handshake to the USB. The MCU clears this bit to end the STALL condition handshake, IN PKT RDY is cleared. The MCU writes a 1 to flush the FIFO. This bit can be set only when OUT_PKT_RDY (D0) is set. The packet due to be unloaded by the MCU will be flushed. Valid only in ISO mode. This bit should be sampled with OUT_PKT_RDY. When set, it indicates the data packet due to be unloaded by the MCU has an error (either bit stuffing or CRC). If two packets are loaded into the FIFO, and the second packet has an error, then this bit gets set only after the first packet is unloaded. This bit is automatically cleared when OUT_PKT_RDY gets cleared. Initial State 0 0 SEND_STALL [5] R/W R 0 FIFO_FLUSH [4] R/W CLEAR 0 DATA_ERROR [3] R R/W 0 OVER_RUN [2] R/ CLEAR R/W Valid only in ISO mode. This bit is set if the core is not able to load an OUT ISO token into the FIFO. The MCU clears this bit by writing 0. - Set by the USB after it has loaded a packet of data into the FIFO. Once the MCU reads the packet from FIFO, this bit should be cleared by MCU (write a "0"). 0 Reserved OUT_PKT_RDY [1] [0] - R/ CLEAR - SET 0 0 13-16 S3C2410X USB DEVICE End Point out Control Status Register (OUT_CSR1_REG/OUT_CSR2_REG) (Continued) Register OUT_CSR2_REG Address 0x52000194(L) 0x52000197(B) R/W R/W (byte) Description End Point out control status register2 Reset Value 0x00 OUT_CSR2_REG AUTO_CLR Bit [7] MCU R/W USB R Description If the MCU is set, whenever the MCU reads data from the OUT FIFO, OUT_PKT_RDY will automatically be cleared by the logic without any intervention from the MCU. Determine endpoint transfer type. 0: Configures endpoint to Bulk mode. 1: Reserved Determine whether the interrupt should be issued or not. OUT_PKT_RDY condition happens. This is only useful for DMA mode 0 = Interrupt Enable 1 = Interrupt Disable Initial State 0 ISO [6] R/W R 0 OUT_DMA_INT_ MASK [5] R/W R 0 13-17 USB DEVICE S3C2410X END POINT FIFO REGISTER (EPN_FIFO_REG) The EPn_FIFO_REG enables the MCU to access to the EPn FIFO. Register EP0_FIFO EP1_FIFO EP2_FIFO EP3_FIFO EP4_FIFO Address 0x520001C0(L) 0x520001C3 (B) 0x520001C4(L) 0x520001C7(B) 0x520001C8(L) 0x520001CB(B) 0x520001CC(L) 0x520001CF(B) 0x520001D0(L) 0x520001D3(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description End Point0 FIFO register End Point1 FIFO register End Point2 FIFO register End Point3 FIFO register End Point4 FIFO register Reset Value 0xXX 0xXX 0xXX 0xXX 0xXX EPn_FIFO FIFO_DATA Bit [7:0] MCU R/W USB R/W FIFO data value Description Initial State 0xXX 13-18 S3C2410X USB DEVICE MAX PACKET REGISTER (MAXP_REG) Register MAXP_REG Address 0x5200018C(L) 0x5200018F(B) R/W R/W (byte) Description End Point MAX packet register Reset Value 0x01 MAXP_REG MAXP Bit [3:0] MCU R/W USB R Description 0000: Reserved 0001: MAXP = 8 Byte0010: MAXP = 16 Byte 0100: MAXP = 32 Byte1000: MAXP = 64 Byte For EP0, MAXP=8 is recommended. For EP1~4, MAXP=32 or MAXP=64 is recommended. And, if MAXP=32, the dual packet mode will be enabled automatically. Initial State 0001 13-19 USB DEVICE S3C2410X END POINT OUT WRITE COUNT REGISTER (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) These registers maintain the number of bytes in the packet as the number is unloaded by the MCU. Register OUT_FIFO_CNT1_ REG Address 0x52000198(L) 0x5200019B(B) R/W R (byte) Description End Point out write count register1 Reset Value 0x00 OUT_FIFO_CNT1_REG OUT_CNT_LOW Bit [7:0] MCU R USB W Description Lower byte of write count Initial State 0x00 Register OUT_FIFO_CNT2_REG Address 0x5200019C(L) 0x5200019F(B) R/W R (byte) Description End Point out write count register2 Reset Value 0x00 OUT_FIFO_CNT2_REG OUT_CNT_HIGH Bit [7:0] MCU R USB W Description Higher byte of write count. The OUT_CNT_HIGH may be always 0 normally. Initial State 0x00 13-20 S3C2410X USB DEVICE DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON) Register EP1_DMA_CON EP2_DMA_CON EP3_DMA_CON EP4_DMA_CON Address 0x52000200(L) 0x52000203(B) 0x52000218(L) 0x5200021B(B) 0x52000240(L) 0x52000243(B) 0x52000258(L) 0x5200025B(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA interface control register EP2 DMA interface control register EP3 DMA interface control register EP4 DMA interface control register Reset Value 0x00 0x00 0x00 0x00 EPn_DMA_CON IN_RUN_OB Bit [7] MCU R/W USB W Description Read) IN_DMA_Run Observation 0: DMA is stopped 1:DMA is running Write) Ignore EPn_DMA_TTC_n register 0: DMA requests will be stopped if EPn_DMA_TTC_n reaches 0. 1: DMA requests will be continued although EPn_DMA_TTC_n reaches 0. Initial State 0 STATE DEMAND_MODE [6:4] [3] R R/W W R DMA State Monitoring DMA Demand mode enable bit 0: Demand mode disable 1: Demand mode enable Functionally separated into write and read operation. Write operation: `0' = Stop `1' = Run Read operation: OUT DMA Run Observation Start DMA operation. 0 = Stop 1 = Run 0 0 OUT_RUN_OB/ OUT_DMA_RUN [2] R/W R/W 0 IN_DMA_RUN DMA_MODE_EN [1] [0] R/W R/W R R/ CLEAR 0 0 Set DMA mode.If the IN_RUN_OB has been wrtten as 0 and EPn_DMA_TTC_n reaches 0, DMA_MODE_EN bit will be cleared by USB. 0 = Interrupt mode 1 = DMA mode 13-21 USB DEVICE S3C2410X DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT) This register is valid in Demand mode. In other modes, this register value must be set to `0x01' Register EP1_DMA_UNIT EP2_DMA_UNIT EP3_DMA_UNIT EP4_DMA_UNIT Address 0x52000204(L) 0x52000207(B) 0x5200021C(L) 0x5200021F(B) 0x52000244(L) 0x52000247(B) 0x5200025C(L) 0x5200025F(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA transfer unit counter base register EP2 DMA transfer unit counter base register EP3 DMA transfer unit counter base register EP4 DMA transfer unit counter base register Reset Value 0x00 0x00 0x00 0x00 DMA_UNIT EPn_UNIT_CNT Bit [7:0] MCU R/W USB R Description EP DMA transfer unit counter value Initial State 0x00 13-22 S3C2410X USB DEVICE DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO) This register has values in byte size in FIFO to be transferred by DMA. In case of OUT_DMA_RUN enabled, the value in OUT FIFO Write Count Register1 will be loaded in this register automatically. In case of IN DMA mode, the MCU should set proper value by software. Register EP1_DMA_FIFO EP2_DMA_FIFO EP3_DMA_FIFO EP4_DMA_FIFO Address 0x52000208(L) 0x5200020B(B) 0x52000220(L) 0x52000223(B) 0x52000248(L) 0x5200024B(B) 0x52000260(L) 0x52000263(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA transfer FIFO counter base register EP2 DMA transfer FIFO counter base register EP3 DMA transfer FIFO counter base register EP4 DMA transfer FIFO counter base register Reset Value 0x00 0x00 0x00 0x00 DMA_FIFO EPn_FIFO_CNT Bit [7:0] MCU R/W USB R Description EP DMA transfer FIFO counter value Initial State 0x00 13-23 USB DEVICE S3C2410X DMA TOTAL TRANSFER COUNTER REGISTER (EPN_DMA_TTC_L,M,H) This register should have total number of bytes to be transferred using DMA (total 20-bit counter). Register EP1_DMA_TTC_L EP1_DMA_TTC_M EP1_DMA_TTC_H EP2_DMA_TTC_L EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_TTC_L EP3_DMA_TTC_M EP3_DMA_TTC_H EP4_DMA_TTC_L EP4_DMA_TTC_M EP4_DMA_TTC_H Address 0x5200020C(L) 0x5200020F(B) 0x52000210(L) 0x52000213(B) 0x52000214(L) 0x52000217(B) 0x52000224(L) 0x52000227(B) 0x52000228(L) 0x5200022B(B) 0x5200022C(L) 0x5200022F(B) 0x5200024C(L) 0x5200024F(B) 0x52000250(L) 0x52000253(B) 0x52000254(L) 0x52000257(B) 0x52000264(L) 0x52000267(B) 0x52000268(L) 0x5200026B(B) 0x5200026C(L) 0x5200026F(B) R/W R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) R/W (byte) Description EP1 DMA total transfer counter(lower byte) EP1 DMA total transfer counter(middle byte) EP1 DMA total transfer counter(higher byte) EP2 DMA total transfer counter(lower byte) EP2 DMA total transfer counter(middle byte) EP2 DMA total transfer counter(higher byte) EP3 DMA total transfer counter(lower byte) EP3 DMA total transfer counter(middle byte) EP3 DMA total transfer counter(higher byte) EP4 DMA total transfer counter(lower byte) EP4 DMA total transfer counter(middle byte) EP4 DMA total transfer counter(higher byte) Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 DMA_TX EPn_TTC_L EPn_TTC_M EPn_TTC_H Bit [7:0] [7:0] [3:0] MCU R/W R/W R/W USB R R R Description DMA total transfer count value (lower byte) DMA total transfer count value (middle byte) DMA total transfer count value (higher byte) Initial State 0x00 0x00 0x00 13-24 S3C2410X INTERRUPT CONTROLLER 14 OVERVIEW INTERRUPT CONTROLLER The interrupt controller in the S3C2410X receives the request from 56 interrupt sources. These interrupt sources are provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt sources, the UARTn and EINTn interrupts are 'OR'ed to the interrupt controller. When receiving multiple interrupt requests from internal peripherals and external interrupt request pins, the interrupt controller requests FIQ or IRQ interrupt of the ARM920T core after the arbitration procedure. The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending register, which helps users notify which interrupt is generated out of various interrupt sources. Request sources (with sub -register) SUBSRCPND SUBMASK SRCPND MASK INTPND Priority Request sources (without sub -register) MODE IRQ FIQ Figure 14-1. Interrupt Process Diagram 14-1 INTERRUPT CONTROLLER S3C2410X INTERRUPT CONTROLLER OPERATION F-bit and I-bit of Program Status Register (PSR) If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request (IRQ) from the interrupt controller. So, the interrupt controller can receive interrupts by clearing F-bit or I-bit of the PSR to 0 and setting the corresponding bit of INTMSK to 0. Interrupt Mode The ARM920T has two types of Interrupt mode: FIQ or IRQ. All the interrupt sources determine which mode is used at interrupt request. Interrupt Pending Register The S3C2410X has two interrupt pending resisters: source pending register (SRCPND) and interrupt pending register (INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service, the corresponding bits of SRCPND register are set to 1, and at the same time, only one bit of the INTPND register is set to 1 automatically after arbitration procedure. If interrupts are masked, the corresponding bits of the SRCPND register are set to 1. This does not cause the bit of INTPND register changed. When a pending bit of the INTPND register is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in the SRCPND register first and then clear the pending condition in the INTPND registers by using the same method. Interrupt Mask Register This register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1. If an interrupt mask bit of INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set. 14-2 S3C2410X INTERRUPT CONTROLLER INTERRUPT SOURCES The interrupt controller supports 56 interrupt sources as shown in the table below. Sources INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD Reserved INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT Reserved EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0 RTC alarm interrupt SPI1 interrupt UART0 Interrupt (ERR, RXD, and TXD) IIC interrupt USB Host interrupt USB Device interrupt Reserved UART1 Interrupt (ERR, RXD, and TXD) SPI0 interrupt SDI interrupt DMA channel 3 interrupt DMA channel 2 interrupt DMA channel 1 interrupt DMA channel 0 interrupt LCD interrupt (INT_FrSyn and INT_FiCnt) UART2 Interrupt (ERR, RXD, and TXD) Timer4 interrupt Timer3 interrupt Timer2 interrupt Timer1 interrupt Timer0 interrupt Watch-Dog timer interrupt RTC Time tick interrupt Battery Fault interrupt Reserved External interrupt 8 - 23 External interrupt 4 - 7 External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 Descriptions ADC EOC and Touch interrupt (INT_ADC/INT_TC) Arbiter Group ARB5 ARB5 ARB5 ARB5 ARB4 ARB4 ARB4 ARB4 ARB4 ARB4 ARB 3 ARB3 ARB3 ARB3 ARB3 ARB3 ARB2 ARB2 ARB2 ARB2 ARB 2 ARB2 ARB1 ARB1 ARB1 ARB1 ARB1 ARB1 ARB0 ARB0 ARB0 ARB0 14-3 INTERRUPT CONTROLLER S3C2410X INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 14-2 below. ARM IRQ ARBITER6 REQ0 REQ1 REQ2 REQ3 REQ4 REQ5 ARBITER0 REQ1/EINT0 REQ2/EINT1 REQ3/EINT2 REQ4/EINT3 ARBITER1 REQ0/EINT4_7 REQ1/EINT8_23 REQ2/reserved REQ3/nBATT_FLT REQ4/INT_TICK REQ5/INT_WDT REQ0/INT_TIMER0 REQ1/INT_TIMER1 REQ2/INT_TIMER2 REQ3/INT_TIMER3 REQ4/INT_TIMER4 REQ5/INT_UART2 REQ0/INT_LCD REQ1/INT_DMA0 REQ2/INT_DMA1 REQ3/INT_DMA2 REQ4/INT_DMA3 REQ5/INT_SDI REQ0/INT_SPI0 REQ1/INT_UART1 REQ2/reserved REQ3/INT_USBD REQ4/INT_USBH REQ5/INT_IIC REQ1/INT_UART0 REQ2/INT_SPI1 REQ3/INT_RTC REQ4/INT_ADC ARBITER2 ARBITER3 ARBITER4 ARBITER5 Figure 14-2. Priority Generating Block 14-4 S3C2410X INTERRUPT CONTROLLER INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows: -- If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. -- If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5. -- If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5. -- If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5. Note that REQ0 of an arbiter always has the highest priority, and REQ5 has the lowest one. In addition, by changing the ARB_SEL bits, we can rotate the priority of REQ1 to REQ4. Here, if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, making the arbiter to operate in the fixed priority mode (note that even in this mode, we can reconfigure the priority by manually changing the ARB_SEL bits). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b automatically so as to put REQ1 into the lowest priority. The detailed rules of ARB_SEL change are as follows: -- If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all. -- If REQ1 is serviced, ARB_SEL bits are changed to 01b. -- If REQ2 is serviced, ARB_SEL bits are changed to 10b. -- If REQ3 is serviced, ARB_SEL bits are changed to 11b. -- If REQ4 is serviced, ARB_SEL bits are changed to 00b. 14-5 INTERRUPT CONTROLLER S3C2410X INTERRUPT CONTROLLER SPECIAL REGISTERS There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending register. They are divided into two groups including Fast Interrupt Request (FIQ) and Interrupt Request (IRQ), based on the interrupt mode register. The arbitration procedure for multiple IRQs is based on the priority register. SOURCE PENDING (SRCPND) REGISTER The SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. Accordingly, this register indicates which interrupt source is waiting for the request to be serviced. Note that each bit of the SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register. In addition, the SRCPND register is not affected by the priority logic of interrupt controller. In the interrupt service routine for a specific interrupt source, the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly. If you return from the ISR without clearing the bit, the interrupt controller operates as if another interrupt request came in from the same source. In other words, if a specific bit of the SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be serviced. The time to clear the corresponding bit depends on the user's requirement. If you want to receive another valid request from the same source, you should clear the corresponding bit first, and then enable the interrupt. You can clear a specific bit of the SRCPND register by writing a data to this register. It clears only the bit positions of the SRCPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are. Register SRCPND Address 0X4A000000 R/W R/W Description Indicate the interrupt request status. 0 = The interrupt has not been requested. 1 = The interrupt source has asserted the interrupt request. Reset Value 0x00000000 14-6 S3C2410X INTERRUPT CONTROLLER SOURCE PENDING (SRCPND) REGISTER (Continued) SRCPND INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD Reserved INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT Reserved EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14-7 INTERRUPT CONTROLLER S3C2410X INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). Note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller (you should use the FIQ mode only for the urgent interrupt). Thus, only one bit of INTMOD can be set to 1. Register INTMOD Address 0X4A000004 R/W R/W Description Interrupt mode regiseter. 0 = IRQ mode 1 = FIQ mode Reset Value 0x00000000 NOTE: If an interrupt mode is set to FIQ mode in the INTMOD register, FIQ interrupt will not affect both INTPND and INTOFFSET registers. In this case, the two registers are valid only for IRQ mode interrupt source. 14-8 S3C2410X INTERRUPT CONTROLLER INTMOD INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD Reserved INT_URRT1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT Reserved EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, Not used 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, Not used 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ Description Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14-9 INTERRUPT CONTROLLER S3C2410X INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced. Register INTMSK Address 0X4A000008 R/W R/W Description Determine which interrupt source is masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available. 1 = Interrupt service is masked. Reset Value 0xFFFFFFFF 14-10 S3C2410X INTERRUPT CONTROLLER INTMSK INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD Reserved INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT Reserved EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, Not used 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, Not used 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked Initial State 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 14-11 INTERRUPT CONTROLLER S3C2410X PRIORITY REGISTER (PRIORITY) Register PRIORITY Address 0x4A00000C R/W R/W Description IRQ priority control register Reset Value 0x7F PRIORITY ARB_SEL6 Bit [20:19] Description Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 5 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 4 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 3 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 2 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 1 group priority order set 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 Arbiter 0 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 6 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 5 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 4 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 3 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 2 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Initial State 0 ARB_SEL5 [18:17] 0 ARB_SEL4 [16:15] 0 ARB_SEL3 [14:13] 0 ARB_SEL2 [12:11] 0 ARB_SEL1 [10:9] 0 ARB_SEL0 [8:7] 0 ARB_MODE6 [6] 1 ARB_MODE5 [5] 1 ARB_MODE4 [4] 1 ARB_MODE3 [3] 1 ARB_MODE2 [2] 1 14-12 S3C2410X INTERRUPT CONTROLLER Priority Register (PRIORITY) (Continued) PRIORITY ARB_MODE1 Bit [1] Description Arbiter 1 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 0 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Initial State 1 ARB_MODE0 [0] 1 14-13 INTERRUPT CONTROLLER S3C2410X INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority . Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU. In interrupt service routine for IRQ, you can read this register to determine which interrupt source is serviced among the 32 sources. Like the SRCPND register, this register has to be cleared in the interrupt service routine after clearing the SRCPND register. We can clear a specific bit of the INTPND register by writing a data to this register. It clears only the bit positions of the INTPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are. Register INTPND Address 0X4A000010 R/W R/W Description Indicate the interrupt request status. 0 = The interrupt has not been requested. 1 = The interrupt source has asserted the interrupt request. Reset Value 0x00000000 NOTES: 1. If the FIQ mode interrupt occurs, the corresponding bit of INTPND will not be turned on as the INTPND register is available only for IRQ mode interrupt. 2. Cautions in clearing the INTPND register. The INTPND register is cleared to `0' by writing `1'. If the INTPND bit, which has `1', is cleared by `0', the INTPND register & INTOFFSET register may have unexpected value in some case. So, you never write `0' on the INTPND bit having `1'. The convenient method to clear the INTPND register is writing the INTPND register value on the INTPND register. (In even our example code, this guide hasn't been applied yet.) 14-14 S3C2410X INTERRUPT CONTROLLER INTPND INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD Reserved INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT Reserved EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14-15 INTERRUPT CONTROLLER S3C2410X INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register INTOFFSET Address 0X4A000014 R/W R Description Indicate the IRQ interrupt request source Reset Value 0x00000000 INT Source INT_ADC INT_RTC INT_SPI1 INT_UART0 INT_IIC INT_USBH INT_USBD Reserved INT_UART1 INT_SPI0 INT_SDI INT_DMA3 INT_DMA2 INT_DMA1 INT_DMA0 INT_LCD The OFFSET Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Source INT_UART2 INT_TIMER4 INT_TIMER3 INT_TIMER2 INT_TIMER1 INT_TIMER0 INT_WDT INT_TICK nBATT_FLT Reserved EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0 The OFFSET Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOTE: FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt. 14-16 S3C2410X INTERRUPT CONTROLLER SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are. Register SUBSRCPND Address 0X4A000018 R/W R/W Description Indicate the interrupt request status. 0 = The interrupt has not been requested. 1 = The interrupt source has asserted the interrupt request. Reset Value 0x00000000 SUBSRCPND Reserved INT_ADC INT_TC INT_ERR2 INT_TXD2 INT_RXD2 INT_ERR1 INT_TXD1 INT_RXD1 INT_ERR0 INT_TXD0 INT_RXD0 Bit [31:11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested Initial State 0 0 0 0 0 0 0 0 0 0 0 0 14-17 INTERRUPT CONTROLLER S3C2410X INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced. Register INTSUBMSK Address 0X4A00001C R/W R/W Description Determine which interrupt source is masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available. 1 = Interrupt service is masked. Reset Value 0x7FF INTSUBMSK Reserved INT_ADC INT_TC INT_ERR2 INT_TXD2 INT_RXD2 INT_ERR1 INT_TXD1 INT_RXD1 INT_ERR0 INT_TXD0 INT_RXD0 Bit [31:11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Not used 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, 0 = Service available, Description 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked 1 = Masked Initial State 0 1 1 1 1 1 1 1 1 1 1 1 14-18 S3C2410X LCD CONTROLLER 15 OVERVIEW LCD CONTROLLER The LCD controller in the S3C2410X consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver. The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome LCD, using a time-based dithering algorithm and Frame Rate Control (FRC) method and it can be interfaced with a color LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color) for interfacing with STN LCD. It can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, and 8-bit per pixel for interfacing with the palettized TFT color LCD panel, and 16-bit per pixel and 24-bit per pixel for non-palettized true-color display. The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate. FEATURES STN LCD displays: -- Supports 3 types of LCD panels: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display type -- Supports the monochrome, 4 gray levels, and 16 gray levels -- Supports 256 colors and 4096 colors for color STN LCD panel -- Supports multiple screen size Typical actual screen size: 640x480, 320x240, 160x160, and others Maximum virtual screen size is 4Mbytes. Maximum virtual screen size in 256 color mode: 4096x1024, 2048x2048, 1024x4096, and others TFT LCD displays: -- Supports 1, 2, 4 or 8-bpp (bit per pixel) palettized color displays for TFT -- Supports 16-bpp non-palettized true-color displays for color TFT -- Supports 24-bpp non-palettized true-color displays for color TFT -- Supports maximum 16M color TFT at 24bit per pixel mode -- Supports multiple screen size Typical actual screen size: 640x480, 320x240, 160x160, and others Maximum virtual screen size is 4Mbytes. Maximum virtual screen size in 64K color mode: 2048x1024 and others 15-1 LCD CONTROLLER S3C2410X COMMON FEATURES The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory. Its features also include: -- Dedicated interrupt functions (INT_FrSyn and INT_FiCnt) -- The system memory is used as the display memory. -- Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling) -- Programmable timing control for different display panels -- Supports little and big-endian byte ordering, as well as WinCE data formats -- Supports SEC TFT LCD panel (SAMSUNG 3.5 Portrait/256K Color/Reflective a-Si TFT LCD) LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit LTS350Q1-PD2: TFT LCD panel only NOTE WinCE doesn't support the 12-bit packed data format. Please check if WinCE can support the 12-bit color-mode. EXTERNAL INTERFACE SIGNAL VFRAME/VSYNC/STV : Frame synchronous signal (STN)/vertical synchronous signal (TFT)/SEC TFT signal VLINE/HSYNC/CPV VCLK/LCD_HCLK VD[23:0] VM/VDEN/TP LEND/STH LCD_PWREN LCDVF0 LCDVF1 LCDVF2 : Line synchronous pulse signal (STN)/horizontal sync signal (TFT)/SEC TFT signal : Pixel clock signal (STN/TFT)/SEC TFT signal : LCD pixel data output ports (STN/TFT/SEC TFT) : AC bias signal for the LCD driver (STN)/data enable signal (TFT)/SEC TFT signal : Line end signal (TFT)/SEC TFT signal : LCD panel power enable control signal : SEC TFT Signal OE : SEC TFT Signal REV : SEC TFT Signal REVB The 33 output ports in total includes 24 data bits and 9 control bits 15-2 S3C2410X LCD CONTROLLER BLOCK DIAGRAM System Bus REGBANK TIMEGEN VIDEO MUX LPC3600 VCLK /LCD_HCLK VLINE / HSYNC / CPV VFRAME / VSYNC / STV VM / VDEN / TP . . . LCDVF0 LCDVF1 LCDVF2 VD[23:0] LCDCDMA VIDPRCS LPC3600 is a timing control logic unit for LTS350Q1-PD1 or LTS350Q1-PD2. Figure 15-1. LCD Controller Block Diagram The S3C2410X LCD controller is used to transfer the video data and to generate the necessary control signals, such as VFRAME, VLINE, VCLK, VM, and so on. In addition to the control signals, the S3C2410X has the data ports for video data, which are VD[23:0] as shown in Figure 15-1. The LCD controller consists of a REGBANK, LCDCDMA, VIDPRCS, TIMEGEN, and LPC3600 (See the Figure 15-1 LCD Controller Block Diagram). The REGBANK has 17 programmable register sets and 256x16 palette memory which are used to configure the LCD controller. The LCDCDMA is a dedicated DMA, which can transfer the video data in frame memory to LCD driver automatically. By using this special DMA, the video data can be displayed on the screen without CPU intervention. The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD[23:0] data ports to the LCD driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. The TIMEGEN consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different LCD drivers. The TIMEGEN block generates VFRAME, VLINE, VCLK, VM, and so on. The description of data flow is as follows: FIFO memory is present in the LCDCDMA. When FIFO is empty or partially empty, the LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode (consecutive memory fetching of 4 words (16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). When the transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal FIFO. The total size of FIFO is 28 words, which consists of 12 words FIFOL and 16 words FIFOH, respectively. The S3C2410X has two FIFOs to support the dual scan display mode. In case of single scan mode, one of the FIFOs (FIFOH) can only be used. 15-3 LCD CONTROLLER S3C2410X STN LCD CONTROLLER OPERATION TIMING GENERATOR (TIMEGEN) The TIMEGEN generates the control signals for the LCD driver, such as VFRAME, VLINE, VCLK, and VM. These control signals are closely related to the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK. Based on these programmable configurations on the LCD control registers in the REGBANK, the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers. The VFRAME pulse is asserted for the duration of the entire first line at a frequency of once per frame. The VFRAME signal is asserted to bring the LCD's line pointer to the top of the display to start over. The VM signal helps the LCD driver alternate the polarity of the row and column voltages, which are used to turn the pixel on and off. The toggling rate of VM signals depends on the MMODE bit of the LCDCON1 register and MVAL field of the LCDCON4 register. If the MMODE bit is 0, the VM signal is configured to toggle on every frame. If the MMODE bit is 1, the VM signal is configured to toggle on the every event of the elapse of the specified number of VLINE by the MVAL[7:0] value. Figure 15-4 shows an example for MMODE=0 and for MMODE=1 with the value of MVAL[7:0]=0x2. When MMODE=1, the VM rate is related to MVAL[7:0], as shown below: VM Rate = VLINE Rate / ( 2 * MVAL) The VFRAME and VLINE pulse generation relies on the configurations of the HOZVAL field and the LINEVAL field in the LCDCON2/3 register. Each field is related to the LCD size and display mode. In other words, the HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation: HOZVAL = (Horizontal display size / Number of the valid VD data line)-1 In color mode: Horizontal display size = 3 * Number of Horizontal Pixel In the 4-bit single scan display mode, the Number of valid VD data line should be 4. In case of 4-bit dual scan display, the Number of valid VD data line should also be 4 while in case of 8-bit single scan display mode, the Number of valid VD data line should be 8. LINEVAL = (Vertical display size) -1: In case of single scan display type LINEVAL = (Vertical display size / 2) -1: In case of dual scan display type The rate of VCLK signal depends on the configuration of the CLKVAL field in the LCDCON1 register. Table 15-1 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 2. VCLK(Hz)=HCLK/(CLKVAL x 2) The frame rate is the VFRAM signal frequency. The frame rate is closely related to the field of WLH[1:0](VLINE pulse width) WDLY[1:0] (the delay width of VCLK after VLINE pulse), HOZVAL, LINEBLANK, and LINEVAL in the LCDCON1/2/3/4 registers as well as VCLK and HCLK. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows: frame_rate(Hz) = 1 / [ { (1/VCLK) x (HOZVAL+1)+(1/HCLK) x (A+B+(LINEBLANK x 8) ) } x ( LINEVAL+1) ] A = 2(4+WLH), B = 2(4+WDLY) 15-4 S3C2410X LCD CONTROLLER Table 15-1. Relation Between VCLK and CLKVAL (STN, HCLK = 60 MHz) CLKVAL 2 3 : 1023 60 MHz/X 60 MHz/4 60 MHz/6 : 60 MHz/2046 VCLK 15.0 MHz 10.0 MHz : 29.3 kHz VIDEO OPERATION The S3C2410X LCD controller supports 8-bit color mode (256 color mode), 12-bit color mode (4096 color mode), 4 level gray scale mode, 16 level gray scale mode as well as the monochrome mode. For the gray or color mode, it is required to implement the shades of gray level or color according to time-based dithering algorithm and Frame Rate Control (FRC) method. The selection can be made following a programmable lockup table, which will be explained later. The monochrome mode bypasses these modules (FRC and lookup table) and basically serializes the data in FIFOH (and FIFOL if a dual scan display type is used) into 4-bit (or 8-bit if a 4-bit dual scan or 8-bit single scan display type is used) streams by shifting the video data to the LCD driver. The following sections describe the operation on the gray and color mode in terms of the lookup table and FRC. Lookup Table The S3C2410X can support the lookup table for various selection of color or gray level mapping, ensuring flexible operation for users. The lookup table is the palette which allows the selection on the level of color or gray (Selection on 4-gray levels among 16 gray levels in case of 4 gray mode, selection on 8 red levels among 16 levels, 8 green levels among 16 levels and 4 blue levels among 16 levels in case of 256 color mode). In other words, users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode. The gray levels cannot be selected in the 16 gray level mode; all 16 gray levels must be chosen among the possible 16 gray levels. In case of 256 color mode, 3 bits are allocated for red, 3 bits for green and 2 bits for blue. The 256 colors mean that the colors are formed from the combination of 8 red, 8 green and 4 blue levels (8x8x4 = 256). In the color mode, the lookup table can be used for suitable selections. Eight red levels can be selected among 16 possible red levels, 8 green levels among 16 green levels, and 4 blue levels among 16 blue levels. In case of 4096 color mode, there is no selection as in the 256 color mode. Gray Mode Operation The S3C2410X LCD controller supports two gray modes: 2-bit per pixel gray (4 level gray scale) and 4-bit per pixel gray (16 level gray scale). The 2-bit per pixel gray mode uses a lookup table (BLUELUT), which allows selection on 4 gray levels among 16 possible gray levels. The 2-bit per pixel gray lookup table uses the BULEVAL[15:0] in Blue Lookup Table (BLUELUT) register as same as blue lookup table in color mode. The gray level 0 will be denoted by BLUEVAL[3:0] value. If BLUEVAL[3:0] is 9, level 0 will be represented by gray level 9 among 16 gray levels. If BLUEVAL[3:0] is 15, level 0 will be represented by gray level 15 among 16 gray levels, and so on. Following the same method as above, level 1 will also be denoted by BLUEVAL[7:4], the level 2 by BLUEVAL[11:8], and the level 3 by BLUEVAL[15:12]. These four groups among BLUEVAL[15:0] will represent level 0, level 1, level 2, and level 3. In 16 gray levels, there is no selection as in the 16 gray levels. 15-5 LCD CONTROLLER S3C2410X 256 Level Color Mode Operation The S3C2410X LCD controller can support an 8-bit per pixel 256 color display mode. The color display mode can generate 256 levels of color using the dithering algorithm and FRC. The 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue. The color display mode uses separate lookup tables for red, green, and blue. Each lookup table uses the REDVAL[31:0] of REDLUT register, GREENVAL[31:0] of GREENLUT register, and BLUEVAL[15:0] of BLUELUT register as the programmable lookup table entries. Similar to the gray level display, 8 group or field of 4 bits in the REDLUR register, i.e., REDVAL[31:28], REDLUT[27:24], REDLUT[23:20], REDLUT[19:16], REDLUT[15:12], REDLUT[11:8], REDLUT[7:4], and REDLUT[3:0], are assigned to each red level. The possible combination of 4 bits (each field) is 16, and each red level should be assigned to one level among possible 16 cases. In other words, the user can select the suitable red level by using this type of lookup table. For green color, the GREENVAL[31:0] of the GREENLUT register is assigned as the lookup table, as was done in the case of red color. Similarly, the BLUEVAL[15:0] of the BLUELUT register is also assigned as a lookup table. For blue color, 2 bits are allocated for 4 blue levels, different from the 8 red or green levels. 4096 Level Color Mode Operation The S3C2410X LCD controller can support a 12-bit per pixel 4096 color display mode. The color display mode can generate 4096 levels of color using the dithering algorithm and FRC. The 12-bit per pixel are encoded into 4bits for red, 4-bits for green, and 4-bits for blue. The 4096 color display mode does not use lookup tables. 15-6 S3C2410X LCD CONTROLLER DITHERING AND FRAME RATE CONTROL For STN LCD displays (except monochrome), video data must be processed by a dithering algorithm. The DITHFRC block has two functions, such as Time-based Dithering Algorithm for reducing flicker and Frame Rate Control (FRC) for displaying gray and color level on the STN panel. The main principle of gray and color level display on the STN panel based on FRC is described. For example, to display the third gray (3/16) level from a total of 16 levels, the 3 times pixel should be on and 13 times pixel off. In other words, 3 frames should be selected among the 16 frames, of which 3 frames should have a pixel-on on a specific pixel while the remaining 13 frames should have a pixel-off on a specific pixel. These 16 frames should be displayed periodically. This is basic principle on how to display the gray level on the screen, so-called gray level display by FRC. The actual example is shown in Table 15-2. To represent the 14th gray level in the table, we should have a 6/7 duty cycle, which mean that there are 6 times pixel-on and one time pixel-off. The other cases for all gray levels are also shown in Table 15-2. In the STN LCD display, we should be reminded of one item, i.e., Flicker Noise due to the simultaneous pixel-on and -off on adjacent frames. For example, if all pixels on first frame are turned on and all pixels on next frame are turned off, the Flicker Noise will be maximized. To reduce the Flicker Noise on the screen, the average probability of pixel-on and -off between frames should be the same. In order to realize this, the Time-based Dithering Algorithm, which varies the pattern of adjacent pixels on every frame, should be used. This is explained in detail. For the 16 gray level, FRC should have the following relationship between gray level and FRC. The 15th gray level should always have pixel-on, and the 14th gray level should have 6 times pixel-on and one times pixeloff, and the 13th gray level should have 4 times pixel-on and one times pixel-off, ,,,,,,,, , and the 0th gray level should always have pixel-off as shown in Table 15-2. Table 15-2. Dither Duty Cycle Examples Pre-Dithered Data (gray level number) 15 14 13 12 11 10 9 8 Duty Cycle 1 6/7 4/5 3/4 5/7 2/3 3/5 4/7 Pre-Dithered Data (gray level number) 7 6 5 4 3 2 1 0 Duty Cycle 1/2 3/7 2/5 1/3 1/4 1/5 1/7 0 15-7 LCD CONTROLLER S3C2410X Display Types The LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. Figure 15-2 shows these 3 different display types for monochrome displays, and Figure 15-3 show these 3 different display types for color displays. 4-bit Dual Scan Display Type A 4-bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time. The 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half, as shown in Figure 15-2. The end of frame is reached when each half of the display has been shifted and transferred. The 8 pins (VD[7:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver. 4-bit Single Scan Display Type A 4-bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. The 4 pins (VD[3:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver, and the 4 pins (VD[7:4]) for the LCD output are not used. 8-bit Single Scan Display Type An 8-bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. The 8 pins (VD[7:0]) for the LCD output from the LCD controller can be directly connected to the LCD driver. 256 Color Displays Color displays require 3 bits (Red, Green, and Blue) of image data per pixel, and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line. resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines. Figure 15-3 shows the RGB and order of the pixels in the parallel data lines for the 3 types of color displays. 4096 Color Displays Color displays require 3 bits (Red, Green, and Blue) of image data per pixel, and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line. This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines. This RGB order is determined by the sequence of video data in video buffers. 15-8 S3C2410X LCD CONTROLLER MEMORY DATA FORMAT (STN, BSWP=0) Mono 4-bit Dual Scan Display: Video Buffer Memory: Address 0000H 0004H * * * Data A[31:0] B[31:0] LCD Panel A[31] A[30] ...... A[0] B[31] B[30] ...... B[0] ...... L[31] L[30] ...... L[0] M[31] M[30] ...... M[0] ...... 1000H 1004H * * * L[31:0] M[31:0] Mono 4-bit Single Scan Display & 8-bit Single Scan Display: Video Buffer Memory: Address Data 0000H A[31:0] 0004H B[31:0] 0008H C[31:0] * * * LCD Panel A[31] A[30] A[29] ...... A[0] B[31] B[30] ...... B[0] C[31] ...... C[0] ...... 15-9 LCD CONTROLLER S3C2410X MEMORY DATA FORMAT ( STN, BSWP=0 ) (CONTINUED) In 4-level gray mode, 2 bits of video data correspond to 1 pixel. In 16-level gray mode, 4 bits of video data correspond to 1 pixel. In 256 level color mode, 8 bits (3 bits of red, 3 bits of green, and 2 bits of blue) of video data correspond to 1 pixel. The color data format in a byte is as follows: Bit [ 7:5 ] Red Bit [ 4:2 ] Green Bit[1:0] Blue In 4096 level color mode, 12 bits (4 bits of red, 4 bits of green, 4 bits of blue) of video data correspond to 1 pixel. The following table shows color data format in words: (Video data must reside at 3 word boundaries (8 pixel), as follows) RGB Order DATA Word #1 Word #2 Word #3 [31:28] Red( 1) Blue(3) Green(6) [27:24] Green(1) Red(4) Blue(6) [23:20] Blue( 1) Green(4) Red(7) [19:16] Red( 2) Blue(4) Green(7) [15:12] Green( 2) Red(5) Blue(7) [11:8] Blue( 2) Green(5) Red(8) [7:4] Red(3) Blue(5) Green(8) [3:0] Green(3) Red(6) Blue(8) 15-10 S3C2410X LCD CONTROLLER VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . 4-bit Dual Scan Display VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . 4-bit Single Scan Display VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 . . . . . . 8-bit Single Scan Display Figure 15-2. Monochrome Display Types (STN) 15-11 LCD CONTROLLER S3C2410X VD3 R1 VD2 G1 1 Pixel VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . VD7 R1 VD6 G1 VD5 B1 VD4 R2 VD7 G2 VD6 B2 VD5 R3 VD4 G3 4-bit Dual Scan Display . . . . . . VD3 R1 VD2 G1 1 Pixel VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 4-bit Single Scan Display . . . . . . VD7 R1 VD6 G1 1 Pixel VD5 B1 VD4 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 8-bit Single Scan Display Figure 15-3. Color Display Types (STN) . . . . . . 15-12 S3C2410X LCD CONTROLLER Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD driver's shift register. After each horizontal line of data has been shifted into the LCD driver's shift register, the VLINE signal is asserted to display the line on the panel. The VM signal provides an AC signal for the display. The LCD uses the signal to alternate the polarity of the row and column voltages, which are used to turn the pixels on and off, because the LCD plasma tends to deteriorate whenever subjected to a DC voltage. It can be configured to toggle on every frame or to toggle every programmable number of VLINE signals. Figure 15-4 shows the timing requirements for the LCD driver interface. 15-13 LCD CONTROLLER S3C2410X Full Frame Timing (MMODE = 0) INT_FrSyn VFRAME VM VLINE LINE1LINE2LINE3 LINE4LINE5LINE6 LINEn LINE1 Full Frame Timing (MMODE = 1, MVAL = 0x2) INT_FrSyn VFRAME VM VLINE LINE1LINE2LINE3 LINE4LINE5LINE6 LINEn LINE1 INT_FrSyn First Line Timing VFRAME VM VLINE LINECNT VCLK WDLY First Line Check & Data Timing VFRAME VM VLINE VCLK VD[7:0] WDLY WLH LINEBLANK WDLY Display the last line of the previous frame LINECNT decreases & Display the 1st line Figure 15-4. 8-bit Single Scan Display Type STN LCD Timing 15-14 S3C2410X LCD CONTROLLER TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK. Base on these programmable configurations on the LCD control registers in the REGBANK, the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers. The VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display. The VSYNC and HSYNC pulse generation depends on the configurations of both the HOZVAL field and the LINEVAL field in the LCDCON2/3 registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations: HOZVAL = (Horizontal display size) -1 LINEVAL = (Vertical display size) -1 The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register. Table 15-3 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 0. VCLK(Hz)=HCLK/[(CLKVAL+1)x2] The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL in LCDCON1 and LCDCON2/3/4 registers. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows: Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ] Table 15-3. Relation Between VCLK and CLKVAL (TFT, HCLK=60 MHz) CLKVAL 1 2 : 1023 60 MHz/X 60 MHz/4 60 MHz/6 : 60 MHz/2048 VCLK 15.0 MHz 10.0 MHz : 30.0 kHz VIDEO OPERATION The TFT LCD controller within the S3C2410X supports 1, 2, 4 or 8 bpp (bit per pixel) palettized color displays and 16 or 24 bpp non-palettized true-color displays. 256 Color Palette The S3C2410X can support the 256 color palette for various selection of color mapping, providing flexible operation for users. 15-15 LCD CONTROLLER S3C2410X MEMORY DATA FORMAT (TFT) This section includes some examples of each display mode. 24BPP Display (BSWP = 0, HWSWP = 0, BPP24BL = 0) D[31:24] 000H 004H 008H ... Dummy Bit Dummy Bit Dummy Bit D[23:0] P1 P2 P3 (BSWP = 0, HWSWP = 0, BPP24BL = 1) D[31:8] 000H 004H 008H ... P1 P2 P3 D[7:0] Dummy Bit Dummy Bit Dummy Bit P1 P2 P3 P4 P5 ...... LCD Panel VD Pin Descriptions at 24BPP VD RED GREEN BLUE 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 15-16 S3C2410X LCD CONTROLLER 16BPP Display (BSWP = 0, HWSWP = 0) D[31:16] 000H 004H 008H ... P1 P3 P5 D[15:0] P2 P4 P6 (BSWP = 0, HWSWP = 1) D[31:16] 000H 004H 008H ... P2 P4 P6 D[15:0] P1 P3 P5 P1 P2 P3 P4 P5 ...... LCD Panel VD Pin Connections at 16BPP (5:6:5) VD RED GREEN BLUE (5:5:5:I) VD RED GREEN BLUE NOTE: The unused VD pins can be used as GPIO. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 4 3 2 1 0 NC 5 4 3 2 1 0 NC 7 6 5 4 3 210 NC 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 4 3 2 1 0 I NC 4 3 2 1 0 I 9 8 765432 1 0 NC 43210 I NC 15-17 LCD CONTROLLER S3C2410X 8BPP Display (BSWP = 0, HWSWP = 0) D[31:24] 000H 004H 008H ... P1 P5 P9 D[23:16] P2 P6 P10 D[15:8] P3 P7 P11 D[7:0] P4 P8 P12 (BSWP = 1, HWSWP = 0) D[31:24] 000H 004H 008H ... P4 P8 P12 D[23:16] P3 P7 P11 D[15:8] P2 P6 P10 D[7:0] P1 P5 P9 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 ...... LCD Panel 15-18 S3C2410X LCD CONTROLLER 4BPP Display (BSWP = 0, HWSWP = 0) D[31:28] 000H 004H 008H ... P1 P9 P17 D[27:24] P2 P10 P18 D[23:20] P3 P11 P19 D[19:16] P4 P12 P20 D[15:12] P5 P13 P21 D[11:8] P6 P14 P22 D[7:4] P7 P15 P23 D[3:0] P8 P16 P24 (BSWP = 1, HWSWP = 0) D[31:28] 000H 004H 008H ... P7 P15 P23 D[27:24] P8 P16 P24 D[23:20] P5 P13 P21 D[19:16] P6 P14 P22 D[15:12] P3 P11 P19 D[11:8] P4 P12 P20 D[7:4] P1 P9 P17 D[3:0] P2 P10 P18 2BPP Display (BSWP = 0, HWSWP = 0) D 000H 004H 008H ... [31:30] P1 P17 P33 [29:28] P2 P18 P34 [27:26] P3 P19 P35 [25:24] P4 P20 P36 [23:22] P5 P21 P37 [21:20] P6 P22 P38 [19:18] P7 P23 P39 [17:16] P8 P24 P40 D 000H 004H 008H ... [15:14] P9 P25 P41 [13:12] P10 P26 P42 [11:10] P11 P27 P43 [9:8] P12 P28 P44 [7:6] P13 P29 P45 [5:4] P14 P30 P46 [3:2] P15 P31 P47 [1:0] P16 P32 P48 15-19 LCD CONTROLLER S3C2410X 256 PALETTE USAGE (TFT) Palette Configuration and Format Control The S3C2410X provides 256 color palette for TFT LCD Control. The user can select 256 colors from the 64K colors in these two formats. The 256 color palette consists of the 256 (depth) x 16-bit SPSRAM. The palette supports 5:6:5 (R:G:B) format and 5:5:5:1(R:G:B:I) format. When the user uses 5:5:5:1 format, the intensity data(I) is used as a common LSB bit of each RGB data. So, 5:5:5:1 format is the same as R(5+I):G(5+I):B(5+I) format. In 5:5:5:1 format, for example, the user can write the palette as in Table 15-5 and then connect VD pin to TFT LCD panel(R(5+I)=VD[23:19]+VD[18], VD[10] or VD[2], G(5+I)=VD[15:11]+ VD[18], VD[10] or VD[2], B(5+I)=VD[7:3]+ VD[18], VD[10] or VD[2].), and set FRM565 of LCDCON5 register to 0. Table 15-4. 5:6:5 Format INDEX\Bit Pos. 00H 01H ....... FFH Number of VD R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 23 22 21 20 19 15 14 13 12 11 10 7 6 5 4 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address 0X4D000400 (note1) R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 0X4D000404 ....... 0X4D0007FC Table 15-5. 5:5:5:1 Format INDEX\Bit Pos. 00H 01H ....... FFH Number of VD R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 23 22 21 20 19 15 14 13 12 11 7 6 5 4 3 I 2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I Address 0X4D000400 0X4D000404 ....... 0X4D0007FC R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 NOTES: 1. 0x4D000400 is Palette start address. 2. VD18, VD10 and VD2 have the same output value, I. 3. DATA[31:16] is invalid. Palette Read/Write When the user performs Read/Write operation on the palette, HSTATUS and VSTATUS of LCDCON5 register must be checked, for Read/Write operation is prohibited during the ACTIVE status of HSTATUS and VSTATUS. Temporary Palette Configuration The S3C2410X allows the user to fill a frame with one color without complex modification to fill the one color to the frame buffer or palette. The one colored frame can be displayed by the writing a value of the color which is displayed on LCD panel to TPALVAL of TPAL register and enable TPALEN. 15-20 S3C2410X LCD CONTROLLER A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I 1 2 3 4 5 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 A[6] R4 B3 B2 B1 B0 I A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:5:5+1 Format(Non-Palette) A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 1 2 3 4 5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 A[15] A[14] A[13] A[12]A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] LCD Panel 16BPP 5:6:5 Format(Non-Palette) Figure 15-5. 16BPP Display Types (TFT) 15-21 LCD CONTROLLER S3C2410X INT_FrSyn VSYNC HSYNC VDEN VBPD+1 VSPW+1 LINEVAL +1 1 Frame VFPD+1 1 Line HSYNC VCLK VD VDEN LEND HBPD+1 HSPW+1 HOZVAL+1 HFPD+1 Figure 15-6. TFT LCD Timing Example 15-22 S3C2410X LCD CONTROLLER SAMSUNG TFT LCD PANEL (3.5 PORTRAIT / 256K COLOR /REFLECTIVE A-SI TFT LCD) The S3C2410X supports SEC TFT LCD panel (SAMSUNG 3.5 Portrait / 256K Color /Reflective a-Si TFT LCD). LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit LTS350Q1-PD2: TFT LCD panel only The S3C2410X provides timing signals as follows to use LTS350Q1-PD1 and PD2: STH: TP: INV: LCD_HCLK: CPV: STV: OE: REV: REVB: Horizontal Start Pulse Source Driver Data Load Pulse Digital Data Inversion Horizontal Sampling Clock Vertical Shift Clock Vertical Start Pulse Gate On Enable Inversion Signal Inversion Signal So, LTS350Q1-PD1 and PD2 can be connected with the S3C2410X without using the additional timing control logic. But the user should additionally apply Vcom generator circuit, various voltages, INV signal and Gray scale voltage generator circuit, which is recommended by PRODUCT INFORMATION (SPEC) of LTS350Q1-PD1 and PD2. Detailed timing diagram is also described in PRODUCT INFORMATION (SPEC) of LTS350Q1-PD1 and PD2. Refer to the documentation (PRODUCT INFORMATION of LTS350Q1-PD1 and PD2), which is prepared by AMLCD Technical Customer Center of Samsung Electronics Co., LTD. Caution: The S3C2410X has HCLK, working as the clock of AHB bus. Accidentally, SEC TFT LCD panel (LTS350Q1-PD1 and PD2) has Horizontal Sampling Clock (HCLK). These two HCLKs may cause a confusion. So, note that HCLK of the S3C2410X is HCLK and other HCLK of the LTS350 is LCD_HCLK. Check that the HCLK of SEC TFT LCD panel (LTS350Q1-PD1 and PD2) is changed to LCD_HCLK. 15-23 LCD CONTROLLER S3C2410X VIRTUAL DISPLAY (TFT/STN) The S3C2410X supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see Figure 15-8), except the values of PAGEWIDTH and OFFSIZE. The video buffer in which the image is stored should be larger than the LCD panel screen in size. OFFSIZE PAGEWIDTH OFFSIZE This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen. LCDBASEU View Port (The same size of LCD panel.) LINEVAL + 1 LCDBASEL This is the data of line 1 of virtual screen. This is the data of line 1 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 2 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 3 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 4 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 5 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 6 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 7 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 8 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 9 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 10 of virtual screen. This is the data of line 11 of virtual screen. This is the data of line 11 of virtual screen. Figure 15-7. Example of Scrolling in Virtual Display (Single Scan) 15-24 . . . . . . Before Scrolling After Scrolling S3C2410X LCD CONTROLLER LCD POWER ENABLE (STN/TFT) The S3C2410X provides Power enable (PWREN) function. When PWREN is set to make PWREN signal enabled, the output value of LCD_PWREN pin is controlled by ENVID. In other words, If LCD_PWREN pin is connected to the power on/off control pin of the LCD panel, the power of LCD panel is controlled by the setting of ENVID automatically. The S3C2410X also supports INVPWREN bit to invert polarity of the PWREN signal. This function is available only when LCD panel has its own power on/off control port and when port is connected to LCD_PWREN pin. ENVID LCD_PWREN LCD Panel ON VFRAME VLINE STN LCD ENVID LCD_PWREN LCD Panel ON VSYNC HSYNC VDEN 1 FRAME TFT LCD Figure 15-8. Example of PWREN Function (PWREN = 1, INVPWREN = 0) 15-25 LCD CONTROLLER S3C2410X LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Register LCDCON1 Address 0X4D000000 R/W R/W Description LCD control 1 register Reset Value 0x00000000 LCDCON1 LINECNT (read only) CLKVAL Bit [27:18] [17:8] Description Provide the status of the line counter. Down count from LINEVAL to 0 Determine the rates of VCLK and CLKVAL[9:0]. STN: VCLK = HCLK / (CLKVAL x 2) ( CLKVAL 2 ) TFT: VCLK = HCLK / [(CLKVAL+1) x 2] ( CLKVAL 0 ) Determine the toggle rate of the VM. 0 = Each Frame, 1 = The rate defined by the MVAL Select the display mode. 00 = 4-bit dual scan display mode (STN) 01 = 4-bit single scan display mode (STN) 10 = 8-bit single scan display mode (STN) 11 = TFT LCD panel Select the BPP (Bits Per Pixel) mode. 0000 = 1 bpp for STN, Monochrome mode 0001 = 2 bpp for STN, 4-level gray mode 0010 = 4 bpp for STN, 16-level gray mode 0011 = 8 bpp for STN, color mode 0100 = 12 bpp for STN, color mode 1000 = 1 bpp for TFT 1001 = 2 bpp for TFT 1010 = 4 bpp for TFT 1011 = 8 bpp for TFT 1100 = 16 bpp for TFT 1101 = 24 bpp for TFT LCD video output and the logic enable/disable. 0 = Disable the video output and the LCD control signal. 1 = Enable the video output and the LCD control signal. Initial State 0000000000 0000000000 MMODE [7] 0 PNRMODE [6:5] 00 BPPMODE [4:1] 0000 ENVID [0] 0 15-26 S3C2410X LCD CONTROLLER LCD Control 2 Register Register LCDCON2 Address 0X4D000004 R/W R/W Description LCD control 2 register Reset Value 0x00000000 LCDCON2 VBPD Bit [31:24] Description TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. STN: These bits should be set to zero on STN LCD. TFT/STN: These bits determine the vertical size of LCD panel. TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. STN: These bits should be set to zero on STN LCD. TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines. STN: These bits should be set to zero on STN LCD. Initial State 0x00 LINEVAL VFPD [23:14] [13:6] 0000000000 00000000 VSPW [5:0] 000000 15-27 LCD CONTROLLER S3C2410X LCD Control 3 Register Register LCDCON3 Address 0X4D000008 R/W R/W Description LCD control 3 register Reset Value 0x00000000 LCDCON3 HBPD (TFT) WDLY (STN) Bit [25:19] Description TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. STN: WDLY[1:0] bits determine the delay between VLINE and VCLK by counting the number of the HCLK. WDLY[7:2] are reserved. 00 = 16 HCLK, 01 = 32 HCLK, 10 = 48 HCLK, 11 = 64 HCLK Initial state 0000000 HOZVAL [18:8] TFT/STN: These bits determine the horizontal size of LCD panel. HOZVAL has to be determined to meet the condition that total bytes of 1 line are 4n bytes. If the x size of LCD is 120 dot in mono mode, x=120 cannot be supported because 1 line consists of 15 bytes. Instead, x=128 in mono mode can be supported because 1 line is composed of 16 bytes (2n). LCD panel driver will discard the additional 8 dot. 00000000000 HFPD (TFT) LINEBLANK (STN) [7:0] TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. STN: These bits indicate the blank time in one horizontal line duration time. These bits adjust the rate of the VLINE finely. The unit of LINEBLANK is HCLK X 8. Ex) If the value of LINEBLANK is 10, the blank time is inserted to VCLK during 80 HCLK. 0X00 15-28 S3C2410X LCD CONTROLLER LCD Control 4 Register Register LCDCON4 Address 0X4D00000C R/W R/W Description LCD control 4 register Reset Value 0x00000000 LCDCON4 MVAL HSPW(TFT) WLH(STN) Bit [15:8] [7:0] Description STN: These bit define the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'. TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. STN: WLH[1:0] bits determine the VLINE pulse's high level width by counting the number of the HCLK. WLH[7:2] are reserved. 00 = 16 HCLK, 01 = 32 HCLK, 10 = 48 HCLK, 11 = 64 HCLK Initial state 0X00 0X00 15-29 LCD CONTROLLER S3C2410X LCD Control 5 Register Register LCDCON5 Address 0X4D000010 R/W R/W Description LCD control 5 register Reset Value 0x00000000 LCDCON5 Reserved VSTATUS Bit [31:17] [16:15] Description This bit is reserved and the value should be '0'. TFT: Vertical Status (read only). 00 = VSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch TFT: Horizontal Status (read only). 00 = HSYNC 01 = BACK Porch 10 = ACTIVE 11 = FRONT Porch TFT: This bit determines the order of 24 bpp video memory. 0 = LSB valid 1 = MSB Valid TFT: This bit selects the format of 16 bpp output video data. 0 = 5:5:5:1 Format 1 = 5:6:5 Format STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge 1 = The video data is fetched at VCLK rising edge STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = Normal 1 = Inverted STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = Normal 1 = Inverted STN/TFT: This bit indicates the VD (video data) pulse polarity. 0 = Normal 1 = VD is inverted. Initial state 0 00 HSTATUS [14:13] 00 BPP24BL FRM565 INVVCLK [12] [11] [10] 0 0 0 INVVLINE [9] 0 INVVFRAME [8] 0 INVVD [7] 0 15-30 S3C2410X LCD CONTROLLER LCD Control 5 Register (Continued) LCDCON5 INVVDEN Bit [6] Description TFT: This bit indicates the VDEN signal polarity. 0 = Normal 1 = Inverted STN/TFT: This bit indicates the PWREN signal polarity. 0 = Normal 1 = Inverted TFT: This bit indicates the LEND signal polarity. 0 = Normal 1 = Inverted STN/TFT: LCD_PWREN output signal enable/disable. 0 = Disable PWREN signal 1 = Enable PWREN signal TFT: LEND output signal enable/disable. 0 = Disable LEND signal 1 = Enable LEND signal STN/TFT: Byte swap control bit. 0 = Swap Disable 1 = Swap Enable STN/TFT: Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable Initial state 0 INVPWREN [5] 0 INVLEND [4] 0 PWREN [3] 0 ENLEND [2] 0 BSWP [1] 0 HWSWP [0] 0 15-31 LCD CONTROLLER S3C2410X FRAME BUFFER START ADDRESS 1 REGISTER Register LCDSADDR1 Address 0X4D000014 R/W R/W Description STN/TFT: Frame buffer start address 1 register Reset Value 0x00000000 LCDSADDR1 LCDBANK Bit [29:21] Description These bits indicate A[30:22] of the bank location for the video buffer in the system memory. LCDBANK value cannot be changed even when moving the view port. LCD frame buffer should be within aligned 4MB region, which ensures that LCDBANK value will not be changed when moving the view port. So, care should be taken to use the malloc() function. For dual-scan LCD: These bits indicate A[21:1] of the start address of the upper address counter, which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD. For single-scan LCD: These bits indicate A[21:1] of the start address of the LCD frame buffer. Initial State 0x00 LCDBASEU [20:0] 0x000000 FRAME Buffer Start Address 2 Register Register LCDSADDR2 Address 0X4D000018 R/W R/W Description STN/TFT: Frame buffer start address 2 register Reset Value 0x00000000 LCDSADDR2 LCDBASEL Bit [20:0] Description For dual-scan LCD: These bits indicate A[21:1] of the start address of the lower address counter, which is used for the lower frame memory of dual scan LCD. For single scan LCD: These bits indicate A[21:1] of the end address of the LCD frame buffer. LCDBASEL = ((the fame end address) >>1) + 1 = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) Initial State 0x0000 NOTE: Users can change the LCDBASEU and LCDBASEL values for scrolling while the LCD controller is turned on. But, users must not change the value of the LCDBASEU and LCDBASEL registers at the end of FRAME by referring to the LINECNT field in LCDCON1 register, for the LCD FIFO fetches the next frame data prior to the change in the frame. So, if you change the frame, the pre-fetched FIFO data will be obsolete and LCD controller will display an incorrect screen. To check the LINECNT, interrupts should be masked. If any interrupt is executed just after reading LINECNT, the read LINECNT value may be obsolete because of the execution time of Interrupt Service Routine (ISR). 15-32 S3C2410X LCD CONTROLLER FRAME Buffer Start Address 3 Register Register LCDSADDR3 Address 0X4D00001C R/W R/W Description STN/TFT: Virtual screen address set Reset Value 0x00000000 LCDSADDR3 OFFSIZE Bit [21:11] Description Virtual screen offset size (the number of half words). This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line. Virtual screen page width (the number of half words). This value defines the width of the view port in the frame. Initial State 00000000000 PAGEWIDTH [10:0] 000000000 NOTE: The values of PAGEWIDTH and OFFSIZE must be changed when ENVID bit is 0. Example 1. LCD panel = 320*240, 16gray, single scan Frame start address = 0x0c500000 Offset dot number = 2048 dots ( 512 half words ) LINEVAL = 240-1 = 0xef PAGEWIDTH = 320*4/16 = 0x50 OFFSIZE = 512 = 0x200 LCDBANK = 0x0c500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0x50 + 0x200 ) * ( 0xef + 1 ) = 0xa2b00 Example 2. LCD panel = 320*240, 16gray, dual scan Frame start address = 0x0c500000 Offset dot number = 2048 dots ( 512 half words ) LINEVAL = 120-1 = 0x77 PAGEWIDTH = 320*4/16 = 0x50 OFFSIZE = 512 = 0x200 LCDBANK = 0x0c500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0x50 + 0x200 ) * ( 0x77 + 1 ) = 0x91580 Example 3. LCD panel = 320*240, color, single scan Frame start address = 0x0c500000 Offset dot number = 1024 dots ( 512 half words ) LINEVAL = 240-1 = 0xef PAGEWIDTH = 320*8/16 = 0xa0 OFFSIZE = 512 = 0x200 LCDBANK = 0x0c500000 >> 22 = 0x31 LCDBASEU = 0x100000 >> 1 = 0x80000 LCDBASEL = 0x80000 + ( 0xa0 + 0x200 ) * ( 0xef + 1 ) = 0xa7600 15-33 LCD CONTROLLER S3C2410X RED Lookup Table Register Register REDLUT Address 0X4D000020 R/W R/W Description STN: Red lookup table register Reset Value 0x00000000 REDLUT REDVAL Bit [31:0] Description These bits define which of the 16 shades will be chosen by each of the 8 possible red combinations. 000 = REDVAL[3:0], 001 = REDVAL[7:4] 010 = REDVAL[11:8], 011 = REDVAL[15:12] 100 = REDVAL[19:16], 101 = REDVAL[23:20] 110 = REDVAL[27:24], 111 = REDVAL[31:28] Initial State 0x00000000 GREEN Lookup Table Register Register GREENLUT Address 0X4D000024 R/W R/W Description STN: Green lookup table register Reset Value 0x00000000 GREENLUT GREENVAL Bit [31:0] Description These bits define which of the 16 shades will be chosen by each of the 8 possible green combinations. 000 = GREENVAL[3:0], 001 = GREENVAL[7:4] 010 = GREENVAL[11:8], 011 = GREENVAL[15:12] 100 = GREENVAL[19:16], 101 = GREENVAL[23:20] 110 = GREENVAL[27:24], 111 = GREENVAL[31:28] Initial State 0x00000000 BLUE Lookup Table Register Register BLUELUT Address 0X4D000028 R/W R/W Description STN: Blue lookup table register Reset Value 0x0000 BULELUT BLUEVAL Bit [15:0] Description These bits define which of the 16 shades will be chosen by each of the 4 possible blue combinations. 00 = BLUEVAL[3:0], 01 = BLUEVAL[7:4] 10 = BLUEVAL[11:8], 11 = BLUEVAL[15:12] Initial State 0x0000 NOTE: Address from 0x14A0002C to 0x14A00048 should not be used. This area is reserved for Test mode. 15-34 S3C2410X LCD CONTROLLER Dithering Mode Register Register DITHMODE Address 0X4D00004C R/W R/W Description STN: Dithering mode register. This register reset value is 0x00000 But, user can change this value to 0x12210. (Refer to a sample program source for the latest value of this register.) Reset Value 0x00000 DITHMODE DITHMODE Bit [18:0] Description Use one of following value for your LCD: 0x00000 or 0x12210 Initial state 0x00000 15-35 LCD CONTROLLER S3C2410X Temp Palette Register Register TPAL Address 0X4D000050 R/W R/W Description TFT: Temporary palette register. This register value will be video data at next frame. Reset Value 0x00000000 TPAL TPALEN TPALVAL Bit [24] [23:0] Description Temporary palette register enable bit. 0 = Disable 1 = Enable Temporary palette value register. TPALVAL[23:16] : RED TPALVAL[15:8] : GREEN TPALVAL[7:0] : BLUE Initial state 0 0x000000 15-36 S3C2410X LCD CONTROLLER LCD Interrupt Pending Register Register LCDINTPND Address 0X4D000054 R/W R/W Description Indicate the LCD interrupt pending register Reset Value 0x0 LCDINTPND INT_FrSyn Bit [1] Description LCD frame synchronized interrupt pending bit. 0 = The interrupt has not been requested. 1 = The frame has asserted the interrupt request. LCD FIFO interrupt pending bit. 0 = The interrupt has not been requested. 1 = LCD FIFO interrupt is requested when LCD FIFO reaches trigger level. Initial state 0 INT_FiCnt [0] 0 LCD Source Pending Register Register LCDSRCPND Address 0X4D000058 R/W R/W Description Indicate the LCD interrupt source pending register Reset Value 0x0 LCDSRCPND INT_FrSyn Bit [1] Description LCD frame synchronized interrupt source pending bit. 0 = The interrupt has not been requested. 1 = The frame has asserted the interrupt request. LCD FIFO interrupt source pending bit. 0 = The interrupt has not been requested. 1 = LCD FIFO interrupt is requested when LCD FIFO reaches trigger level. Initial state 0 INT_FiCnt [0] 0 15-37 LCD CONTROLLER S3C2410X LCD Interrupt Mask Register Register LCDINTMSK Address 0X4D00005C R/W R/W Description Determine which interrupt source is masked. The masked interrupt source will not be serviced. Reset Value 0x3 LCDINTMSK FIWSEL INT_FrSyn Bit [2] [1] Description Determine the trigger level of LCD FIFO. 0 = 4 words 1 = 8 words Mask LCD frame synchronized interrupt. 0 = The interrupt service is available. 1 = The interrupt service is masked. Mask LCD FIFO interrupt. 0 = The interrupt service is available. 1 = The interrupt service is masked. Initial state 1 INT_FiCnt [0] 1 LPC3600 Control Register Register LPCSEL Address 0X4D000060 R/W R/W Description This register controls the LPC3600 modes. Reset Value 0x4 LPCSEL RES_SEL LPC_EN Bit [1] [0] 1 = 240x320 Description Determine LPC3600 Enable/Disable. 0 = LPC3600 Disable 1 = LPC3600 Enable Initial state 0 0 15-38 S3C2410X LCD CONTROLLER Register Setting Guide (STN) The LCD controller supports multiple screen sizes by special register setting. The CLKVAL value determines the frequency of VCLK. This value has to be determined such that the VCLK value is greater than data transmission rate. The data transmission rate for the VD port of the LCD controller is used to determine the value of CLKVAL register. The data transmission rate is given by the following equation: Data transmission rate = HS x VS x FR x MV HS: VS: FR: MV: Horizontal LCD size Vertical LCD size Frame rate Mode dependent value Table 15-6. MV Value for Each Display Mode Mode Mono, 4-bit single scan display Mono, 8-bit single scan display or 4-bit dual scan display 4 level gray, 4-bit single scan display 4 level gray, 8-bit single scan display or 4-bit dual scan display 16 level gray, 4-bit single scan display 16 level gray, 8-bit single scan display or 4-bit dual scan display Color, 4-bit single scan display Color, 8-bit single scan display or 4-bit dual scan display MV Value 1/4 1/8 1/4 1/8 1/4 1/8 3/4 3/8 The LCDBASEU register value is the first address value of the frame buffer. The lowest 4 bits must be eliminated for burst 4 word access. The LCDBASEL register value depends on LCD size and LCDBASEU. The LCDBASEL value is given by the following equation: LCDBASEL = LCDBASEU + LCDBASEL offset 15-39 LCD CONTROLLER S3C2410X Example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, HCLK frequency is 60 MHz WLH = 1, WDLY = 1. Data transmission rate = 160 x 160 x 80 x 1/4 = 512 kHz CLKVAL = 58, VCLK = 517 kHz HOZVAL = 39, LINEVAL = 159 LINEBLANK =10 LCDBASEL = LCDBASEU + 3200 NOTE: The higher the system load is, the lower the cpu performance is. Example 2 (Virtual Screen Register): 4 -level gray, Virtual screen size = 1024 x 1024, LCD size = 320 x 240, LCDBASEU = 0x64, 4-bit dual scan. 1 halfword = 8 pixels (4-level gray), Virtual screen 1 line = 128 halfword = 1024 pixels, LCD 1 line = 320 pixels = 40 halfword, OFFSIZE = 128 - 40 = 88 = 0x58, PAGEWIDTH = 40 = 0x28 LCDBASEL = LCDBASEU + (PAGEWIDTH + OFFSIZE) x (LINEVAL +1) = 100 + (40 + 88) x 120 = 0 x 3C64 15-40 S3C2410X LCD CONTROLLER Gray Level Selection Guide The S3C2410X LCD controller can generate 16 gray level using Frame Rate Control (FRC). The FRC characteristics may cause unexpected patterns in gray level. These unwanted erroneous patterns may be shown in fast response LCD or at lower frame rates. Because the quality of LCD gray levels depends on LCD's own characteristics, the user has to select an appropriate gray level after viewing all gray levels on user's own LCD. Select the gray level quality through the following procedures: 1. Get the latest dithering pattern register value from SAMSUNG. 2. Display 16 gray bar in LCD. 3. Change the frame rate into an optimal value. 4. Change the VM alternating period to get the best quality. 5. As viewing 16 gray bars, select a good gray level, which is displayed well on your LCD. 6. Use only the good gray levels for quality. LCD Refresh Bus Bandwidth Calculation Guide The S3C2410X LCD controller can support various LCD display sizes. To select a suitable size (for the flicker free LCD system application), the user have to consider the LCD refresh bus bandwidth determined by the LCD display size, bit per pixel (bpp), frame rate, memory bus width, memory type, and so on. LCD Data Rate (Byte/s) = bpp x (Horizontal display size) x (Vertical display size) x (Frame rate) /8 LCD DMA Burst Count (Times/s) = LCD Data Rate(Byte/s) /16(Byte) ; LCD DMA using 4words(16Byte) burst Pdma means LCD DMA access period. In other words, the value of Pdma indicates the period of four-beat burst (4-words burst) for video data fetch. So, Pdma depends on memory type and memory setting. Eventually, LCD System Load is determined by LCD DMA Burst Count and Pdma. LCD System Load = LCD DMA Burst Count x Pdma Example 3: 640 x 480, 8bpp, 60 frame/sec, 16-bit data bus width, SDRAM (Trp=2HCLK / Trcd=2HCLK / CL=2HCLK) and HCLK frequency is 60 MHz LCD Data Rate = 8 x 640 x 480 x 60 / 8 = 18.432Mbyte/s LCD DMA Burst Count = 18.432 / 16 = 1.152M/s Pdma = (Trp+Trcd+CL+(2 x 4)+1) x (1/60 MHz) = 0.250ms LCD System Load = 1.152 x 250 = 0.288 System Bus Occupation Rate = (0.288/1) x 100 = 28.8% 15-41 LCD CONTROLLER S3C2410X Register Setting Guide (TFT LCD) The CLKVAL register value determines the frequency of VCLK and frame rate. Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ] For applications, the system timing must be considered to avoid under-run condition of the fifo of the lcd controller caused by memory bandwidth contention. Example 4: TFT Resolution: 240 x 240, VSPW = 2, VBPD = 14, LINEVAL = 239, VFPD = 4 HSPW = 25, HBPD = 15, HOZVAL = 239, HFPD = 1 CLKVAL = 5 HCLK = 60M (Hz) The parameters below must be referenced by LCD size and driver specifications: VSPW, VBPD, LINEVAL, VFPD, HSPW, HBPD, HOZVAL, and HFPD If target frame rate is 60-70Hz, then CLKVAL should be 5. So, Frame Rate = 67Hz Known Problems Problem : In a MDS, such as Multi-ICE, some of the LCD controller registers may be displayed incorrectly in the memory view window of the ARM debugger. Solution : The LCD controller register will be displayed correctly unless the memory view window is used. Instead, use 'pr' command in the debugger console window. 15-42 S3C2410X A/D CONVERTER AND TOUCH SCREEN 16 OVERVIEW ADC & TOUCH SCREEN INTERFACE The 10-bit CMOS analog to digital converter (ADC) of the S3C2410X is a recycling typed device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.5 MHz A/D converter clock. The A/D converter operates with on-chip, sample-and-hold function and power down mode is supported. The S3C2410X supports Touch Screen Interface, which consists of a touch screen panel, four external transistors, an external voltage source, AIN[7] and AIN[5] (see Figure 16-2). Touch Screen Interface controls and selects control signals (nYPON, YMON, nXPON and XMON) and analog pads (AIN[7], AIN[5]) which are connected with pads of touch screen panel and the external transistor for Xposition conversion and Y-position conversion. Touch Screen Interface contains an external transistor control logic and an ADC interface logic with an interrupt generation logic. FEATURES -- Resolution: 10-bit -- Differential Linearity Error: 1.5 LSB -- Integral Linearity Error: 2.0 LSB -- Maximum Conversion Rate: 500 KSPS -- Low Power Consumption -- Power Supply Voltage: 3.3V -- Analog Input Range: 0 ~ 3.3V -- On-chip Sample-and-hold Function -- Normal Conversion Mode -- Separate X/Y position conversion Mode -- Auto (Sequential) X/Y Position Conversion Mode -- Waiting for Interrupt Mode 16-1 A/D CONVERTER AND TOUCH SCREEN S3C2410X ADC & TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16-1 shows the functional block diagram of the S3C2410X A/D converter and Touch Screen Interface. Note that the A/D converter is a recycling type. A pull-up resister is attached to AIN[7] on VDDA_ADC. So, XP pad of the touch screen panel should be connected with AIN[7] of the S3C2410X and YP pad of the touch screen panel should be connected with AIN[5]. EINT[23] EINT[22] EINT[21] EINT[20] VDDA_ADC AIN[7] AIN[6] AIN[5] AIN[4] AIN[3] AIN[2] AIN[1] AIN[0] VSSA_ADC nYPON YMON nXPON XMON External Transistor Control 8:1 MUX A/D Convert ADC Interface &Touch Screen Controller INT_ADC ADC Input Control Waiting for Interrupt Mode Interrupt Generation INT_TC Figure 16-1. ADC and Touch Screen Interface Functional Block Diagram 16-2 S3C2410X A/D CONVERTER AND TOUCH SCREEN EXAMPLE FOR TOUCH SCREEN In this example, AIN[7] is connected with XP and AIN[5]is connected with YP pad of the touch screen panel. To control pads of the touch screen panel (XP, XM, YP and YM), four external transistors are applied and control signals including nYPON, YMON, nXPON and XMON are connected with four external transistors. EINT[23] EINT[22] EINT[21] EINT[20] External Voltage Source nYPON YMON nXPON XMON External Transistor Control XP XM YP YM A[7] A[5] Touch Panel S3C2410X01 Figure 16-2. Example of ADC and Touch Screen Interface The following procedure is suggested: 1. Connect pads of the touch screen panel to the S3C2410X using external transistor (see Figure 16-2). 2. Select Separate X/Y Position Conversion Mode or Auto (Sequential) X/Y Position Conversion Mode to get X/Y position. 3. Set Touch Screen Interface to Waiting Interrupt Mode, 4. If interrupt occurs, then appropriate conversion (Separate X/Y Position Conversion Mode or Auto (Sequential) X/Y Position Conversion Mode) is activated. 5. After get the proper value about X/Y position, return to Waiting for Interrupt Mode. NOTES: 1. External voltage source should be 3.3 V. 2. Internal resistance of the external transistor should be under 5 ohm. 16-3 A/D CONVERTER AND TOUCH SCREEN S3C2410X FUNCTION DESCRIPTIONS A/D Conversion Time When the PCLK frequency is 50 MHz and the prescaler value is 49, total 10-bit conversion time is given: A/D converter freq. = 50 MHz/(49+1) = 1 MHz Conversion time = 1/(1 MHz / 5cycles) = 1/200 kHz = 5 us NOTE This A/D converter is designed to operate at maximum 2.5 MHz clock, so the conversion rate can go up to 500 KSPS. Touch Screen Interface Mode 1. Normal Conversion Mode Normal Conversion Mode (AUTO_PST = 0, XY_PST = 0) is generally used for General Purpose ADC Conversion. This mode can be initialized by setting the ADCCON and ADCTSC and completed with a read the XPDATA (Normal ADC) value of ADCDAT0 (ADC Data Register 0). 2. Separate X/Y Position Conversion Mode Separate X/Y Position Conversion Mode is consist of two Conversion Modes: X-Position Mode and Y-Position Mode. The first mode is operated in the following way: X-Position Mode (AUTO_PST = 0 and XY_PST = 1) writes X-position conversion data to XPDATA of ADCDAT0 register. After conversion, The Touch Screen Interface generates the Interrupt source (INT_ADC) to Interrupt Controller. Y-Position Mode (AUTO_PST = 0 and XY_PST = 2) writes Y-position conversion data to YPDATA of ADCDAT1. After the conversion, the Touch Screen Interface also generates the Interrupt source (INT_ADC) to Interrupt Controller. Table 16-1. Condition of Touch Screen Panel Pads in Separate X/Y Position Conversion Mode XP X Position Conversion Y Position Conversion External Voltage AIN[7] XM GND Hi-Z YP AIN[5] External Voltage YM Hi-Z GND 16-4 S3C2410X A/D CONVERTER AND TOUCH SCREEN 3. Auto (Sequential) X/Y Position Conversion Mode. Auto (Sequential) X/Y Position Conversion Mode (AUTO_PST = 1 and XY_PST = 0) is operated in the following way: The Touch Screen Controller automatically converts X-position and Y-position. The Touch Screen Controller writes X-measurement data to XPDATA of ADCDAT0, and then writes Y-measurement data to YPDATA of ADCDAT1. After Auto (Sequential) Position Conversion, The Touch Screen Controller generates Interrupt source (INT_ADC) to Interrupt Controller. Table 16-2. Condition of Touch Screen Panel Pads in Auto (Sequential) X/Y Position Conversion Mode. XP X Position Conversion Y Position Conversion External Voltage AIN[7] XM GND Hi-Z YP AIN[5] External Voltage YM Hi-Z GND 4. Waiting for Interrupt Mode. When Touch Screen Controller is in Waiting for Interrupt Mode, it waits for Stylus down. The controller generates Interrupt (INT_TC) signals when the Stylus is down on Touch Screen Panel. After an interrupt occurs, X and Y position can be read by the proper conversion mode (Separate X/Y position conversion Mode or Auto X/Y Position Conversion Mode). Table 16-3. Condition of Touch Screen Panel Pads in Waiting for Interrupt Mode. XP Waiting for Interrupt Mode Pull-up XM Hi-Z YP AIN[5] YM GND Standby Mode Standby mode is activated when STDBM of ADCCON register is set to '1'. In this mode, A/D conversion operation is halted and XPDATA (Normal ADC) of ADCDAT0 and YPDATA of ADCDAT1 contain the previous converted data. 16-5 A/D CONVERTER AND TOUCH SCREEN S3C2410X Programming Notes 1. The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method, the overall conversion time - from A/D converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time. With polling method, by checking the ADCCON[15] - end of conversion flag-bit, the read time from ADCDAT register can be determined. 2. A/D conversion can be activated in different way: After ADCCON[1] - A/D conversion start-by-read mode-is set to 1, A/D conversion starts simultaneously whenever converted data is read. X-Conversion XP Stylus Down Y-Conversion Stylus Up YP A B C A = D x (1/X-Tal Clock) or A = D x (1/External Clock) B = D x (1/PCLK) C = D x (1/PCLK) D = DELAY value of ADCDLY Register Figure 16-3 Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode 16-6 S3C2410X A/D CONVERTER AND TOUCH SCREEN ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL (ADCCON) REGISTER Register ADCCON Address 0x58000000 R/W R/W Description ADC control register Reset Value 0x3FC4 ADCCON ECFLG Bit [15] Description End of conversion flag (read only). 0 = A/D conversion in process 1 = End of A/D conversion A/D converter prescaler enable. 0 = Disable 1 = Enable A/D converter prescaler value. Data value: 1 ~ 255 Note that division factor is (N+1) when the prescaler value is N. Analog input channel select. 000 = AIN 0 001 = AIN 1 010 = AIN 2 011 = AIN 3 100 = AIN 4 101 = AIN 5 110 = AIN 6 111 = AIN 7 (XP) Standby mode select. 0 = Normal operation mode 1 = Standby mode A/D conversion start by read. 0 = Disable start by read operation 1 = Enable start by read operation A/D conversion starts by setting this bit. If READ_START is enabled, this value is not valid. 0 = No operation 1 = A/D conversion starts and this bit is cleared after the start-up. Initial State 0 PRSCEN [14] 0 PRSCVL [13:6] 0xFF SEL_MUX [5:3] 0 STDBM [2] 1 READ_ START ENABLE_ START [1] 0 [0] 0 16-7 A/D CONVERTER AND TOUCH SCREEN S3C2410X ADC TOUCH SCREEN CONTROL (ADCTSC) REGISTER Register ADCTSC Address 0x58000004 R/W R/W Description ADC touch screen control register Reset Value 0x058 ADCTSC Reserved YM_SEN Bit [8] [7] This bit should be zero. Description Select output value of YMON. 0 = YMON output is 0 (YM = Hi-Z). 1 = YMON output is 1 (YM = GND). Select output value of nYPON. 0 = nYPON output is 0 (YP = External voltage). 1 = nYPON output is 1 (YP is connected with AIN[5]). Select output value of XMON. 0 = XMON output is 0 (XM = Hi-Z). 1 = XMON output is 1 (XM = GND). Select output value of nXPON. 0 = nXPON output is 0 (XP = External voltage). 1 = nXPON output is 1 (XP is connected with AIN[7]). Pull-up switch enable. 0 = XP pull-up enable 1 = XP pull-up disable Automatically sequencing conversion of X-position and Y-position 0 = Normal ADC conversion 1 = Auto (Sequential) X/Y Position Conversion Mode Manual measurement of X-position or Y-position. 00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode Initial State 0 0 YP_SEN [6] 1 XM_SEN [5] 0 XP_SEN [4] 1 PULL_UP [3] 1 AUTO_PST [2] 0 XY_PST [1:0] 0 NOTE: In Auto mode, ADCTSC register should be reconfigured before starting read operation. 16-8 S3C2410X A/D CONVERTER AND TOUCH SCREEN ADC START DELAY (ADCDLY) REGISTER Register ADCDLY Address 0x58000008 R/W R/W Description ADC start or interval delay register Reset Value 0x00ff ADCDLY DELAY Bit [15:0] Description 1) Normal Conversion Mode, Separate X/Y Position Conversion Mode, and Auto (Sequential) X/Y Position Conversion Mode. X/Y Position Conversion Delay Value. 2) Waiting for Interrupt Mode. When Stylus down occurs in Waiting for Interrupt Mode, this register generates Interrupt signal (INT_TC) at intervals of several ms for Auto X/Y Position conversion. NOTE: Do not use Zero value (0x0000) Initial State 00ff NOTES: 1. Before ADC conversion, Touch screen uses X-tal clock or EXTCLK (Waiting for Interrupt Mode). 2. During ADC conversion, PCLK is used. 16-9 A/D CONVERTER AND TOUCH SCREEN S3C2410X ADC CONVERSION DATA (ADCDAT0) REGISTER Register ADCDAT0 Address 0x5800000C R/W R Description ADC conversion data register Reset Value - ADCDAT0 UPDOWN Bit [15] Description Up or down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state 1 = Stylus up state Automatic sequencing conversion of X-position and Y-position. 0 = Normal ADC conversion 1 = Sequencing measurement of X-position, Y-position Manual measurement of X-position or Y-position. 00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode Reserved X-position conversion data value. (include Normal ADC conversion data value) Data value: 0 ~ 3FF Initial State - AUTO_PST [14] - XY_PST [13:12] - Reserved XPDATA (Normal ADC) [11:10] [9:0] - 16-10 S3C2410X A/D CONVERTER AND TOUCH SCREEN ADC CONVERSION DATA (ADCDAT1) REGISTER Register ADCDAT1 Address 0x58000010 R/W R Description ADC conversion data register Reset Value - ADCDAT1 UPDOWN Bit [15] Description Up or down state of Stylus at Waiting for Interrupt Mode. 0 = Stylus down state 1 = Stylus up state Automatically sequencing conversion of X-position and Y-position. 0 = Normal ADC conversion 1 = Sequencing measurement of X-position, Y-position Manual measurement of X-position or Y-position. 00 = No operation mode 01 = X-position measurement 10 = Y-position measurement 11 = Waiting for Interrupt Mode Reserved Y-position conversion data value Data value: 0 ~ 3FF Initial State - AUTO_PST [14] - XY_PST [13:12] - Reserved YPDATA [11:10] [9:0] - 16-11 A/D CONVERTER AND TOUCH SCREEN S3C2410X NOTES 16-12 S3C2410X REAL TIME CLOCK (RTC) 17 OVERVIEW FEATURES REAL TIME CLOCK (RTC) The Real Time Clock (RTC) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as Binary Coded Decimal (BCD) values using the STRB/LDRB ARM operation. The data include the time by second, minute, hour, date, day, month, and year. The RTC unit works with an external 32.768 kHz crystal and also can perform the alarm function. -- BCD number: second, minute, hour, date, day, month, and year -- Leap year generator -- Alarm function: alarm interrupt or wake-up from power-off mode -- Year 2000 problem is removed. -- Independent power pin (RTCVDD) -- Supports millisecond tick time interrupt for RTOS kernel time tick. -- Round reset function 17-1 REAL TIME CLOCK (RTC) S3C2410X REAL TIME CLOCK OPERATION TICNT Time Tick Generator 128 Hz 215 Clock Divider XTIrtc RTCRST Reset Register Leap Year Generator TIME TICK 1 Hz XTOrtc SEC MIN HOUR DATE DAY MON YEAR Control Register RTCCON Alarm Generator RTCALM PMWKUP PWDN ALMINT Figure 17-1. Real Time Clock Block Diagram LEAP YEAR GENERATOR The leap year generator can determine the last date of each month out of 28, 29, 30, or 31, based on data from BCDDATE, BCDMON, and BCDYEAR. This block considers leap year in deciding on the last date. An 8-bit counter can only represent 2 BCD digits, so it cannot decide whether "00" year (the year with its last two digits zeros) is a leap year or not. For example, it cannot discriminate between 1900 and 2000. To solve this problem, the RTC block in S3C2410X has hard-wired logic to support the leap year in 2000. Note 1900 is not leap year while 2000 is leap year. Therefore, two digits of 00 in S3C2410X denote 2000, not 1900. 17-2 S3C2410X REAL TIME CLOCK (RTC) READ/WRITE REGISTERS Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block. To display the second, minute, hour, date, month, and year, the CPU should read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDAY, BCDDATE, BCDMON, and BCDYEAR registers, respectively, in the RTC block. However, a one second deviation may exist because multiple registers are read. For example, when the user reads the registers from BCDYEAR to BCDMIN, the result is assumed to be 2059 (Year), 12 (Month), 31 (Date), 23 (Hour) and 59 (Minute). When the user read the BCDSEC register and the value ranges from 1 to 59 (Second), there is no problem, but, if the value is 0 sec., the year, month, date, hour, and minute may be changed to 2060 (Year), 1 (Month), 1 (Date), 0 (Hour) and 0 (Minute) because of the one second deviation that was mentioned. In this case, the user should re-read from BCDYEAR to BCDSEC if BCDSEC is zero. BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery, which supplies the power through the RTCVDD pin into the RTC block, even if the system power is off. When the system is off, the interfaces of the CPU and RTC logic should be blocked, and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation. ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power-off mode or normal operation mode. In normal operation mode, the alarm interrupt (ALMINT) is activated. In the power-off mode, the power management wakeup (PMWKUP) signal is activated as well as the ALMINT. The RTC alarm register (RTCALM) determines the alarm enable/disable status and the condition of the alarm time setting. TICK TIME INTERRUPT The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches '0' when the tick time interrupt occurs. Then the period of interrupt is as follows: Period = ( n+1 ) / 128 second n: Tick time count value (1~127) This RTC time tick may be used for real time operating system (RTOS) kernel time tick. If time tick is generated by the RTC time tick, the time related function of RTOS will always synchronized in real time. ROUND RESET FUNCTION The round reset function can be performed by the RTC round reset register (RTCRST). The round boundary (30, 40, or 50 sec.) of the second carry generation can be selected, and the second value is rounded to zero in the round reset. For example, when the current time is 23:37:47 and the round boundary is selected to 40 sec, the round reset changes the current time to 23:38:00. NOTE All RTC registers have to be accessed for each byte unit using the STRB and LDRB instructions or char type pointer. 17-3 REAL TIME CLOCK (RTC) S3C2410X 32.768KHZ X-TAL CONNECTION EXAMPLE The Figure 17-2 shows a circuit of the RTC unit oscillation at 32.768 kHz. 15~ 22pF XTIrtc 32768Hz XTOrtc Figure 17-2. Main Oscillator Circuit Example 17-4 S3C2410X REAL TIME CLOCK (RTC) REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, so it should be set to 1 in an RTC control routine to enable data read/write after a system reset. Also before power off, the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers. Register RTCCON Address 0x57000040(L) 0x57000043(B) R/W Description Reset Value 0x0 R/W RTC control register (by byte) RTCCON CLKRST CNTSEL Bit [3] [2] RTC clock count reset. 0 = No reset, 1 = Reset Description Initial State 0 0 BCD count select. 0 = Merge BCD counters 1 = Reserved (Separate BCD counters) BCD clock select. 0 = XTAL 1/215 divided clock 1 = Reserved (XTAL clock only for test) RTC control enable. 0 = Disable 1 = Enable NOTE: Only BCD time count and read operation can be performed. CLKSEL [1] 0 RTCEN [0] 0 NOTES: 1. All RTC registers have to be accessed for each byte unit using STRB and LDRB instructions or char type pointer. 2. (L): Little endian. (B): Big endian. TICK TIME COUNT (TICNT) REGISTER Register TICNT Address 0x57000044(L) 0x57000047(B) R/W Description Reset Value 0x0 R/W Tick time count register (by byte) TICNT TICK INT ENABLE TICK TIME COUNT Bit [7] [6:0] Description Tick time interrupt enable. 0 = Disable 1 = Enable Tick time count value (1~127). This counter value decreases internally, and users cannot read this counter value in working. Initial State 0 000000 17-5 REAL TIME CLOCK (RTC) S3C2410X RTC ALARM CONTROL (RTCALM) REGISTER The RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, but only through ALMINT in the normal operation mode. Register RTCALM Address 0x57000050(L) 0x57000053(B) R/W Description Reset Value 0x0 R/W RTC alarm control register (by byte) RTCALM Reserved ALMEN YEAREN MONREN DATEEN HOUREN MINEN SECEN Bit [7] [6] [5] [4] [3] [2] [1] [0] Alarm global enable. 0 = Disable, 1 = Enable Year alarm enable. 0 = Disable, 1 = Enable Month alarm enable. 0 = Disable, 1 = Enable Date alarm enable. 0 = Disable, 1 = Enable Hour alarm enable. 0 = Disable, 1 = Enable Minute alarm enable. 0 = Disable, 1 = Enable Second alarm enable. 0 = Disable, 1 = Enable Description Initial State 0 0 0 0 0 0 0 0 17-6 S3C2410X REAL TIME CLOCK (RTC) ALARM SECOND DATA (ALMSEC) REGISTER Register ALMSEC Address 0x57000054(L) 0x57000057(B) R/W Description Reset Value 0x0 R/W Alarm second data register (by byte) ALMSEC Reserved SECDATA Bit [7] [6:4] [3:0] Description BCD value for alarm second. 0~5 0~9 Initial State 0 000 0000 ALARM MIN DATA (ALMMIN) REGISTER Register ALMMIN Address 0x57000058(L) 0x5700005B(B) R/W Description Reset Value 0x00 R/W Alarm minute data register (by byte) ALMMIN Reserved MINDATA Bit [7] [6:4] [3:0] Description BCD value for alarm minute. 0~5 0~9 Initial State 0 000 0000 ALARM HOUR DATA (ALMHOUR) REGISTER Register ALMHOUR Address 0x5700005C(L) 0x5700005F(B) R/W Description Reset Value 0x0 R/W Alarm hour data register (by byte) ALMHOUR Reserved HOURDATA Bit [7:6] [5:4] [3:0] BCD value for alarm hour. 0~2 0~9 Description Initial State 00 00 0000 17-7 REAL TIME CLOCK (RTC) S3C2410X ALARM DATE DATA (ALMDATE) REGISTER Register ALMDATE Address 0x57000060(L) 0x57000063(B) R/W Description Reset Value 0x01 R/W Alarm date data register (by byte) ALMDAY Reserved DATEDATA Bit [7:6] [5:4] [3:0] Description BCD value for alarm date, from 0 to 28, 29, 30, 31. 0~3 0~9 Initial State 00 00 0001 ALARM MON DATA (ALMMON) REGISTER Register ALMMON Address 0x57000064(L) 0x57000067(B) R/W Description Reset Value 0x01 R/W Alarm month data register (by byte) ALMMON Reserved MONDATA Bit [7:5] [4] [3:0] BCD value for alarm month. 0~1 0~9 Description Initial State 00 0 0001 ALARM YEAR DATA (ALMYEAR) REGISTER Register ALMYEAR Address 0x57000068(L) 0x5700006B(B) R/W Description Reset Value 0x0 R/W Alarm year data register (by byte) ALMYEAR YEARDATA Bit [7:0] BCD value for year. 00 ~ 99 Description Initial State 0x0 17-8 S3C2410X REAL TIME CLOCK (RTC) RTC ROUND RESET (RTCRST) REGISTER Register RTCRST Address 0x5700006C(L) 0x5700006F(B) R/W Description Reset Value 0x0 R/W RTC round reset register (by byte) RTCRST SRSTEN SECCR Bit [3] [2:0] Round second reset enable. 0 = Disable, 1 = Enable Description Initial State 0 000 Round boundary for second carry generation. 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec NOTE: If other values (0, 1, 2, 6, or 7) are set, no second carry is generated. But second value can be reset. BCD SECOND (BCDSEC) REGISTER Register BCDSEC Address 0x57000070(L) 0x57000073(B) R/W Description Reset Value Undefined R/W BCD second register (by byte) BCDSEC SECDATA Bit [6:4] [3:0] BCD value for second. 0~5 0~9 Description Initial State - BCD MINUTE (BCDMIN) REGISTER Register BCDMIN Address 0x57000074(L) 0x57000077(B) R/W Description Reset Value Undefined R/W BCD minute register (by byte) BCDMIN MINDATA Bit [6:4] [3:0] BCD value for minute. 0~5 0~9 Description Initial State - 17-9 REAL TIME CLOCK (RTC) S3C2410X BCD HOUR (BCDHOUR) REGISTER Register BCDHOUR Address 0x57000078(L) 0x5700007B(B) R/W Description Reset Value Undefined R/W BCD hour register (by byte) BCDHOUR Reserved HOURDATA Bit [7:6] [5:4] [3:0] BCD value for hour. 0~2 0~9 Description Initial State - BCD DATE (BCDDATE) REGISTER Register BCDDATE Address 0x5700007C(L) 0x5700007F(B) R/W Description Reset Value Undefined R/W BCD date register (by byte) BCDDATE Reserved DATEDATA Bit [7:6] [5:4] [3:0] BCD value for date. 0~3 0~9 Description Initial State - BCD DAY (BCDDAY) REGISTER Register BCDDAY Address 0x57000080(L) 0x57000083(B) R/W Description Reset Value Undefined R/W BCD a day of the week register (by byte) BCDDAY Reserved DAYDATA Bit [7:3] [2:0] Description BCD value for a day of the week. 1~7 Initial State - 17-10 S3C2410X REAL TIME CLOCK (RTC) BCD MONTH (BCDMON) REGISTER Register BCDMON Address 0x57000084(L) 0x57000087(B) R/W Description Reset Value Undefined R/W BCD month register (by byte) BCDMON Reserved MONDATA Bit [7:5] [4] [3:0] BCD value for month. 0~1 0~9 Description Initial State - BCD YEAR (BCDYEAR) REGISTER Register BCDYEAR Address 0x57000088(L) 0x5700008B(B) R/W Description Reset Value Undefined R/W BCD year register (by byte) BCDYEAR YEARDATA Bit [7:0] BCD value for year. 00 ~ 99 Description Initial State - 17-11 REAL TIME CLOCK (RTC) S3C2410X NOTES 17-12 S3C2410X WATCHDOG TIMER 18 OVERVIEW FEATURES WATCHDOG TIMER The S3C2410X watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates the reset signal for 128 PCLK cycles. -- Normal interval timer mode with interrupt request -- Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 (time-out). 18-1 WATCHDOG TIMER S3C2410X WATCHDOG TIMER OPERATION Figure 18-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again. MUX 1/16 1/32 PCLK 8-bit Prescaler 1/64 1/128 WTDAT Interrupt WTCNT (Down Counter) Reset Signal Generator RESET WTCON[15:8] WTCON[4:3] WTCON[2] WTCON[0] Figure 18-1. Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control (WTCON) register. Valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64, or 128. Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor ) WTDAT & WTCNT Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically reloaded into the timer counter (WTCNT). In this reason, an initial value must be written to the watchdog timer count (WTCNT) register, before the watchdog timer starts. CONSIDERATION OF DEBUGGING ENVIRONMENT When the S3C2410X is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal (DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated as the watchdog timer is expired. 18-2 S3C2410X WATCHDOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL (WTCON) REGISTER The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The Watchdog timer is used to resume the S3C2410X restart on mal-function after its power on; if controller restart is not desired, the Watchdog timer should be disabled. If the user wants to use the normal timer provided by the Watchdog timer, enable the interrupt and disable the Watchdog timer. Register WTCON Address 0x53000000 R/W R/W Description Watchdog timer control register Reset Value 0x8021 WTCON Prescaler Value Reserved Watchdog Timer Bit [15:8] [7:6] [5] Description Prescaler value. The valid range is from 0 to (28-1). Reserved. These two bits must be 00 in normal operation. Enable or disable bit of Watchdog timer. 0 = Disable 1 = Enable Determine the clock division factor. 00: 16 01: 32 10: 64 11: 128 Enable or disable bit of the interrupt. 0 = Disable 1 = Enable Reserved. This bit must be 0 in normal operation. Enable or disable bit of Watchdog timer output for reset signal. 1: Assert reset signal of the S3C2410X at watchdog time-out 0: Disable the reset function of the watchdog timer. Initial State 0x80 00 1 Clock Select [4:3] 00 Interrupt Generation Reserved Reset Enable/Disable [2] 0 [1] [0] 0 1 18-3 WATCHDOG TIMER S3C2410X WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time-out. In this case, the value of WTDAT will be automatically reloaded into WTCNT. Register WTDAT Address 0x53000004 R/W R/W Description Watchdog timer data register Reset Value 0x8000 WTDAT Count Reload Value Bit [15:0] Description Watchdog timer count value for reload. Initial State 0x8000 WATCHDOG TIMER COUNT (WTCNT) REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation. Note that the content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the WTCNT register must be set to an initial value before enabling it. Register WTCNT Address 0x53000008 R/W R/W Description Watchdog timer count register Reset Value 0x8000 WTCNT Count Value Bit [15:0] Description The current count value of the watchdog timer Initial State 0x8000 18-4 S3C2410X SECURE DIGITAL INTERFACE FOR SDIO (SDI) 19 OVERVIEW FEATURES SECURE DIGITAL INTERFACE FOR SDIO(SDI) The S3C2410X Secure Digital Interface (SDI) can interface for SD memory card, SDIO device and Multi-Media Card (MMC). -- SD Memory Card Spec. (ver. 1.0) / MMC Spec. (2.11) compatible -- SDIO Card Spec (ver. 1.0) compatible -- 16 words (64 bytes) FIFO (depth 16) for data Tx/Rx -- 40-bit Command Register (SDICARG[31:0]+SDICCON[7:0]) -- 136-bit Response Register (SDIRSPn[127:0]+ SDICSTA[7:0]) -- 8-bit Prescaler logic (Freq. = System Clock / (2(P + 1))) -- CRC7 & CRC16 Generator -- Normal, and DMA Data Transfer Mode (byte or word transfer) -- 1bit / 4bit (wide bus) Mode & Block / Stream Mode Switch support -- Supports up to 25 MHz in data transfer mode for SDI -- Supports up to 10 MHz in data transfer mode for MMC 19-1 SECURE DIGITAL INTERFACE FOR SDIO (SDI) S3C2410X BLOCK DIAGRAM 32 PADDR 32 PSEL PCLK APB I/F 32 32 32 32 CMD Reg (5byte) Resp Reg (17byte) 8 CMD Control TxCMD 8bit Shift Reg 8 CRC7 RxCMD Prescaler DAT Control 32bit Shift Reg CRC16*4 SDCLK PWDATA [31:0] PRDATA [31:0] 32 FIFO (64byte) 32 TxDAT[3:0] RxDAT[3:0] DREQ DACK INT DMA INT Figure 19-1. Block Diagram 19-2 S3C2410X SECURE DIGITAL INTERFACE FOR SDIO (SDI) SDI OPERATION A serial clock line is synchronized with the five data lines for shifting and sampling of the information. Making the appropriate bit settings to the SDIPRE register depends on the transmission frequency. You can modify its frequency to adjust the baud rate data register value. Programming Procedure (common) SDI modules can be programmed, following these basic steps: 1. Set SDICON to configure properly with clock and interrupt. 2. Set SDIPRE to configure with a proper value. 3. Wait 74 SDCLK clock cycle in order to initialize the card. CMD Path Programming 1. Write command argument (32-bit) to SDICARG register. 2. Determine command types and start command by setting SDICCON[8]. 3. Confirm the end of SDI command operation when the specific flag of SDICSTA is set. -- If the type of command is no-response, the flag is SDICSTA[11]. -- If the type of command is with-response, the flag is SDICSTA[9]. 4. Clear the corresponding flag of the SDICSTA register by writing one to the flag bit. DAT Path Programming 1. Write timeout period to SDIDTIMER register. 2. Write block size (block length) to SDIBSIZE register (normally 0x200 byte). 3. Determine the mode of block, wide bus, DMA, etc. and start data transfer with setting SDIDCON register. 4. Write Tx-data to SDIDAT register while Tx FIFO is available by checking SDIFSTA (available, half or empty) register. 5. Read Rx-data from SDIDAT register while Rx FIFO is available by checking SDIFSTA (available, half or be last data) register. 6. Confirm the end of SDI data operation when the flag of data transfer finish (SDIDSTA[4]) is set. 7. Clear the corresponding flag of SDIDSTA register by writing one to the flag bit. NOTES 1. In case of MMC, the maximum clock for data transfer is 10 MHz. 2. In MMC write mode, the CRC error is occurred in spite of correct writing. If user wants to transmit data reliably, read the data and compare it after writing. 3. In case of long response, the CRC error should be detected after receiving exact response data from SD device. User should check the CRC of received response by software. 19-3 SECURE DIGITAL INTERFACE FOR SDIO (SDI) S3C2410X SDIO OPERATION There are two functions of the SDIO operation: SDIO Interrupt receiving and Read Wait Request generation. These two functions can operate when RcvIOInt bit and RwaitEn bit of SDICON register is activated respectively. Detailed steps and conditions for the two functions are described below. SDIO Interrupt In SD 1bit mode, the interrupt is received through all ranges from SDDAT1 pin. In SD 4bit mode, SDDAT1 pin is shared between to receive data and interrupts. When interrupt detection ranges (Interrupt Period) are: 1. Single Block: the time between A and B -- A: 2clocks after the completion of a data packet -- B: The completion of sending the end bit of the next with-data command 2. Multi Block, SDIDCON[21] = 0: the time between A and B, restart interrupt detection range at C -- A: 2clocks after the completion of a data packet -- B: 2clocks after A -- C: 2clocks after the end bit of the abort command response 3. Multi Block, SDIDCON[21] = 1: the time between A and B, restart at A -- A: 2clocks after the completion of a data packet -- B: 2clocks after A In case of last block, interrupt period begins at last A, but it does not end at B (CMD53 case). Read Wait Request Regardless of 1bit or 4bit mode, Read Wait Request signal transmits to SDDAT2 pin in the condition below. -- In read multiple operation, request signal transmission begins at 2clocks after the end of the data block. -- Transmission ends when the user writes one to SDIDSTA[10]. 19-4 S3C2410X SECURE DIGITAL INTERFACE FOR SDIO (SDI) SDI SPECIAL REGISTERS SDI Control (SDICON) Register Register SDICON Address 0x5A000000 R/W R/W Description SDI control register Reset Value 0x0 SDICON Byte Order Type (ByteOrder) Receive SDIO Interrupt from card (RcvIOInt) Read Wait Enable (RWaitEn) Bit [4] Description Determine byte order type when you read (write) data from (to) SD host FIFO with word boundary. 0 = Type A, 1 = Type B Determine whether SD host receives SDIO Interrupt from the card or not (for SDIO). 0 = ignore, 1 = receive SDIO Interrupt Determine read wait request signal generate when SD host waits the next block in multiple block read mode. This bit needs to delay the next block to be transmitted from the card (for SDIO). 0 = disable (no generate), 1 = Read wait enable (use SDIO) Reset FIFO value. This bit is automatically cleared. 0 = normal mode, 1 = FIFO reset Determine whether SDCLK Out enable or not. 0 = disable (prescaler off), 1 = clock enable Initial Value 0 [3] 0 [2] 0 FIFO Reset (FRST) Clock Out Enable (ENCLK) [1] [0] 0 0 NOTE: Byte Order Type - Type A: D[7:0] D[15:8] D[23:16] D[31:24] - Type B: D[31:24] D[23:16] D[15:8] D[7:0] SDI Baud Rate Prescaler (SDIPRE) Register Register SDIPRE Address 0x5A000004 R/W R/W Description SDI baud rate prescaler register Reset Value 0x0 SDIPRE Prescaler Value Bit [7:0] Description Determine SDI clock (SDCLK) rate as above equation. Baud rate = PCLK / 2 / (Prescaler value + 1) Initial Value 0x00 19-5 SECURE DIGITAL INTERFACE FOR SDIO (SDI) S3C2410X SDI Command Argument Register (SDICARG) Register SDICARG Address 0x5A000008 R/W R/W Description SDI command argument register Reset Value 0x0 SDICARG CmdArg Bit [31:0] Command Argument Description Initial Value 0x00000000 SDI Command Control (SDICCON) Register Register SDICCON Address 0x5A00000C R/W R/W Description SDI command control register Reset Value 0x0 SDICCON Abort Command (AbortCmd) Command with Data (WithData) LongRsp WaitRsp Command Start(CMST) CmdIndex Bit [12] [11] [10] [9] [8] [7:0] Description Determine whether command type is for abort (for SDIO). 0 = normal command, 1 = abort command (CMD12, CMD52) Determine whether command type is with data (for SDIO). 0 = without data, 1 = with data Determine whether host receives a 136-bit long response or not. 0 = short response, 1 = long response Determine whether host waits for a response or not. 0 = no response, 1 = wait response Determine whether command operation starts or not. 0 = command ready, 1 = command start Command index with start 2bit (8bit) Initial Value 0 0 0 0 0 0x00 19-6 S3C2410X SECURE DIGITAL INTERFACE FOR SDIO (SDI) SDI Command Status (SDICSTA) Register Register SDICSTA Address 0x5A000010 R/W R/(W) Description SDI command status register Reset Value 0x0 SDICSTA Response CRC Fail(RspCrc) Command Sent (CmdSent) Command Time Out (CmdTout) Response Receive End (RspFin) CMD line progress On (CmdOn) RspIndex Bit [12] R/W [11] R/W [10] R/W [9] R/W [8] R [7:0] R Description CRC check failed when command response received. This flag is cleared by setting one to this bit. 0 = not detect, 1 = crc fail Command sent (not concerned with response). This flag is cleared by setting one to this bit. 0 = not detect, 1 = command end Command response timeout (64clk). This flag is cleared by setting one to this bit. 0 = not detect, 1 = timeout Command response received. This flag is cleared by setting one to this bit. 0 = not detect, 1 = response end Command transfer in progress. 0 = not detect, 1 = in progress Response index 6bit with start 2bit (8bit) Initial Value 0 0 0 0 0 0x00 19-7 SECURE DIGITAL INTERFACE FOR SDIO (SDI) S3C2410X SDI Response Register 0 (SDIRSP0) Register SDIRSP0 Address 0x5A000014 R/W R Description SDI response register 0 Reset Value 0x0 SDIRSP0 Response0 Bit [31:0] Description Card status[31:0](short), card status[127:96](long) Initial Value 0x00000000 SDI Response Register 1 (SDIRSP1) Register SDIRSP1 Address 0x5A000018 R/W R Description SDI response register 1 Reset Value 0x0 SDIRSP1 RCRC7 Response1 Bit [31:24] [23:0] Description CRC7 (with end bit, short), card status[95:88](long) Unused (short), card status[87:64](long) Initial Value 0x00 0x000000 SDI Response Register 2 (SDIRSP2) Register SDIRSP2 Address 0x5A00001C R/W R Description SDI response register 2 Reset Value 0xy0 SDIRSP2 Response2 Bit [31:0] Description Unused (short), card status[63:32](long) Initial Value 0x00000000 SDI Response Register 3 (SDIRSP3) Register SDIRSP3 Address 0x5A000020 R/W R Description SDI response register 3 Reset Value 0x0y SDIRSP3 Response3 Bit [31:0] Description Unused (short), card status[31:0](long) Initial Value 0x00000000 19-8 S3C2410X SECURE DIGITAL INTERFACE FOR SDIO (SDI) SDI Data / Busy Timer (SDIDTIMER) Register Register SDIDTIMER SDIDTIMER DataTimer Address 0x5A000024 Bit [15:0] R/W R/W Description SDI data / busy timer register Description Data / busy timeout period (0~65535 cycle) Reset Value 0x2000 Initial Value 0x2000 SDI Block Size (SDIBSIZE) Register Register SDIBSIZE SDIBSIZE BlkSize Address 0x5A000028 Bit [11:0] R/W R/W Description SDI block size register Description Block size value (0~4095 byte). Do not care when stream mode Reset Value 0x0 Initial Value 0x000 NOTE: In Case of multi block, BlkSize must be aligned to word(4byte) size.(BlkSize[1:0] = 00) 19-9 SECURE DIGITAL INTERFACE FOR SDIO (SDI) S3C2410X SDI Data Control (SDIDCON) Register Register SDIDCON SDIDCON SDIO Interrupt Period Type (PrdType) Transmit After Response (TARSP) Address 0x5A00002C Bit [21] R/W R/W Description SDI data control register Description Determine whether SDIO Interrupt period is 2 cycle or extend more cycle when last data block is transferred (for SDIO). 0 = exactly 2 cycle, 1 = more cycle(likely single block) Determine when data transmit start after response receive or not. 0 = directly after DatMode set, 1 = after response receive(assume DatMode sets to 2'b11) Determine when data receive start after command sent or not. 0 = directly after DatMode set, 1 = after command sent (assume DatMode sets to 2'b10) Determine when busy receive start after command sent or not. 0 = directly after DatMode set, 1 = after command sent (assume DatMode sets to 2'b01) Data transfer mode. 0 = stream data transfer, 1 = block data transfer 0 Reset Value 0x0 Initial Value 0 [20] 0 Receive After Command (RACMD) Busy After Command (BACMD) Block mode (BlkMode) Wide bus enable (WideBus) DMA Enable (EnDMA) Stop by force (STOP) Data Transfer Mode (DatMode) BlkNum [19] 0 [18] 0 [17] [16] 0 Determine enable wide bus mode. 0 = standard bus mode(only SDIDAT[0] used), 1 = wide bus mode(SDIDAT[3:0] used) Enable DMA. 0 = disable(polling), 1 = dma enable [15] [14] [13:12] 0 0 00 Determine whether data transfer stop by force or not. 0 = normal, 1 = stop by force Determine the direction of data transfer. 00 = ready, 01 = only busy check start 10 = data receive start, 11 = data transmit start Block Number (0~4095). Do not care when stream mode. [11:0] 0x000 NOTES: 1. If you want one of TARSP, RACMD and BACMD bits (SDIDCON[20:18]) to "1", you need to write on SDIDCON register head of on SDICCON register (always need for SDIO). 2. When DMA operation is completed, DMA Enable[15] bit of SDIDCON register should be disabled. 19-10 S3C2410X SECURE DIGITAL INTERFACE FOR SDIO (SDI) SDI Data Remain Counter (SDIDCNT) Register Register SDIDCNT Address 0x5A000030 R/W R Description SDI data remain counter register Reset Value 0x0 SDIDCNT BlkNumCnt BlkCnt Bit [23:12] [11:0] Remaining block number Description Remaining data byte of 1 block Initial Value 0x000 0x000 19-11 SECURE DIGITAL INTERFACE FOR SDIO (SDI) S3C2410X SDI Data Status (SDIDSTA) Register Register SDIDSTA Address 0x5A000034 R/W R/(W) Description SDI data status register Reset Value 0x0 SDIDSTA Read Wait Request Occur (RWaitReq) SDIO Interrupt Detect (IOIntDet) FIFO Fail error (FFfail) Bit [10] R/W Description Read wait request signal transmits to SD card. The request signal is stopped and this flag is cleared by setting one to this bit.(for SDIO) 0 = not occur, 1 = Read wait request occur SDIO interrupt detects. This flag is cleared by setting one to this bit.(for SDIO) 0 = not detect, 1 = SDIO interrupt detect FIFO fail error when FIFO occurs overrun / underrun / misaligned data saving. This flag is cleared by setting one to this bit. 0 = not detect, 1 = FIFO fail CRC Status error when data block sent (CRC check failed returned from card). This flag is cleared by setting one to this bit. 0 = not detect, 1 = crc status fail Data block received error (CRC check failed - calculated by host). This flag is cleared by setting one to this bit. 0 = not detect, 1 = receive crc fail Data / Busy receive timeout. This flag is cleared by setting one to this bit. 0 = not detect, 1 = timeout Data transfer completes (data counter is zero). This flag is cleared by setting one to this bit. 0 = not detect, 1 = data finish detect Only busy check finish. This flag is cleared by setting one to this bit. 0 = not detect, 1 = busy finish detect Start bit is not detected on all data signals in wide bus mode. This flag is cleared by setting one to this bit. 0 = not detect, 1 = command end Data transmit in progress. 0 = not active, 1 = data Tx in progress Data receive in progress. 0 = not active, 1 = data Rx in progress Initial Value 0 [9] R/W [8] R/W 0 0 CRC Status Fail (CrcSta) [7] R/W 0 Data Receive CRC Fail (DatCrc) Data Time Out (DatTout) Data Transfer Finish (DatFin) Busy Finish (BusyFin) Start Bit Error (SbitErr) Tx Data progress On (TxDatOn) Rx Data Progress On (RxDatOn) [6] R/W [5] R/W [4] R/W [3] R/W [2] R/W [1] R [0] R 0 0 0 0 0 0 0 19-12 S3C2410X SECURE DIGITAL INTERFACE FOR SDIO (SDI) SDI FIFO Status (SDIFSTA) Register Register SDIFSTA Address 0x5A000038 R/W R Description SDI FIFO status register Reset Value 0x0 SDIFSTA FIFO available Detect for Tx (TFDET) FIFO available Detect for Rx (RFDET) Tx FIFO Half Full (TFHalf) Tx FIFO Empty (TFEmpty) Rx FIFO Last Data Ready (RFLast) Rx FIFO Full (RFFull) Rx FIFO Half Full (RFHalf) FIFO Count (FFCNT) Bit [13] Description Indicate that FIFO data is available for transmission when DatMode (SDIDCON[12]) is data transmit mode. If DMA mode is enable, SD host requests DMA operation. 0 = not detect (FIFO full), 1 = detect(0 FIFO 63) Indicate that FIFO data is available for reception when DatMode (SDIDCON[12]) is data receive mode. If DMA mode is enable, SD host requests DMA operation. 0 = not detect(FIFO empty), 1 = detect(1 FIFO 64) Set to 1 whenever Tx FIFO is less than 33byte. 0 = 33 Tx FIFO 64, 1 = 0 Tx FIFO 32 Set to 1 whenever Tx FIFO is empty. 0 = 1 Tx FIFO 64, 1 = Empty(0byte) Set to 1 whenever Rx FIFO has last data of all block. 0 = not received yet, 1 = Last data ready Set to 1 whenever Rx FIFO is full. 0 = 0 Rx FIFO 63, 1 = Full(64byte) Set to 1 whenever Rx FIFO is more than 31byte. 0 = 0 Rx FIFO 31, 1 = 32 Rx FIFO 64 Number of data (byte) in FIFO Initial State 0 [12] 0 [11] [10] [9] [8] [7] [6:0] 0 0 0 0 0 0000000 19-13 SECURE DIGITAL INTERFACE FOR SDIO (SDI) S3C2410X SDI Data (SDIDAT) Register Register SDIDAT Address 0x5A00003C(Li/W, Li/B, Bi/W) 0x5A00003F(Bi/B) Bit [31:0] R/W R/W SDI data register Description Reset Value 0x0 SDIDAT Data Register Description This field contains the data to be transmitted or received over the SDI channel. Initial State 0x00000000 NOTES: 1. (Li/W, Li/B): Access by Word/Byte unit when endian mode is Little 2. (Bi/W): Access by Word unit when endian mode is Big 3. (Bi/B) : Access by Byte unit when endian mode is Big 19-14 S3C2410X SECURE DIGITAL INTERFACE FOR SDIO (SDI) SDI Interrupt Mask (SDIIMSK) Register Register SDIIMSK Address 0x5A000040 R/W R/W Description SDI interrupt mask register Reset Value 0x0 SDIIMSK RspCrc Interrupt Enable CmdSent Interrupt Enable CmdTout Interrupt Enable RspEnd Interrupt Enable RWaitReq Interrupt Enable IOIntDet Interrupt Enable FFfail Interrupt Enable CrcSta Interrupt Enable DatCrc Interrupt Enable DatTout Interrupt Enable DatFin Interrupt Enable BusyFin Interrupt Enable SBitErr Interrupt Enable TFHalf Interrupt Enable TFEmpty Interrupt Enable RFLast Interrupt Enable RFFull Interrupt Enable RFHalf Interrupt Enable Bit [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description Response CRC error interrupt. 0 = disable, 1 = interrupt enable Command sent(without response) interrupt. 0 = disable, 1 = interrupt enable Command response timeout interrupt. 0 = disable, 1 = interrupt enable Command response received interrupt. 0 = disable, 1 = interrupt enable Read wait request interrupt. 0 = disable, 1 = interrupt enable SD host receives SDIO Interrupt from the card (for SDIO). 0 = disable, 1 = interrupt enable FIFO fail error interrupt. 0 = disable, 1 = interrupt enable CRC status errors interrupt. 0 = disable, 1 = interrupt enable Data CRC fail interrupt. 0 = disable, 1 = interrupt enable Data timeout interrupt. 0 = disable, 1 = interrupt enable Data counter zero interrupt. 0 = disable, 1 = interrupt enable Busy checks complete interrupt. 0 = disable, 1 = interrupt enable Start bit error interrupt. 0 = disable, 1 = interrupt enable Tx FIFO half interrupt. 0 = disable, 1 = interrupt enable Tx FIFO empty interrupt. 0 = disable, 1 = interrupt enable Rx FIFO has last data interrupt. 0 = disable, 1 = interrupt enable Rx FIFO full interrupt. 0 = disable, 1 = interrupt enable Rx FIFO half interrupt. 0 = disable, 1 = interrupt enable Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19-15 SECURE DIGITAL INTERFACE FOR SDIO (SDI) S3C2410X SDI Data/Busy Timer Register SDI data/ busy timer register has 16-bit counter. In case of 25MHz operation, the countable maximum time is 2.6ms (40ns * 0x10000). But, some cards have very long access time (TAAC), their TAAC are up to 100ms. In this case the SDI generates data timeout error state. To solve this problem follow the below flow chart. Start Read (multil or single block) Is timeout occurs? Yes 25MHz or 600KHz ? 25MHz Send stop command No Send stop command if multi block Change SDI clock to 600KHz Retry Change SDI clock to 25MHz if 600KHz 600KHz Real-timeout error Return Return error 19-16 S3C2410X IIC-BUS INTERFACE 20 OVERVIEW IIC-BUS INTERFACE The S3C2410X RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directional. In multi-master IIC-bus mode, multiple S3C2410X RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C2410X can initiate and terminate a data transfer over the IIC-bus. The IICbus in the S3C2410X uses Standard bus arbitration procedure. To control multi-master IIC-bus operations, values must be written to the following registers: -- Multi-master IIC-bus control register, IICCON -- Multi-master IIC-bus control/status register, IICSTAT -- Multi-master IIC-bus Tx/Rx data shift register, IICDS -- Multi-master IIC-bus address register, IICADD When the IIC-bus is free, the SDA and SCL lines should be both at High level. A High-to-Low transition of SDA can initiate a Start condition. A Low-to-High transition of SDA can initiate a Stop condition while SCL remains steady at High Level. The Start and Stop conditions can always be generated by the master devices. A 7-bit address value in the first data byte, which is put onto the bus after the Start condition has been initiated, can determine the slave device which the bus master device has selected. The 8th bit determines the direction of the transfer (read or write). Every data byte put onto the SDA line should be eight bits in total. The bytes can be unlimitedly sent or received during the bus transfer operation. Data is always sent from most-significant bit (MSB) first, and every byte should be immediately followed by an acknowledge (ACK) bit. 20-1 IIC-BUS INTERFACE S3C2410X Address Register Comparator IIC-Bus Control Logic SCL PCLK IICCON IICSTAT 4-bit Prescaler Shift Register SDA Shift Register (IICDS) Data Bus Figure 20-1. IIC-Bus Block Diagram NOTE: IIC Data Hold Time The IIC data hold time(tSDAH) is minimum 0ns. (IIC data hold time is minimum 0ns for standard/fast bus mode in IIC specification v2.1.) Please check the data hold time of your IIC device if it's 0 nS or not. The IIC controller supports only IIC bus device(standard/fast bus mode), not C bus device. 20-2 S3C2410X IIC-BUS INTERFACE IIC-BUS INTERFACE The S3C2410X IIC-bus interface has four operation modes: -- Master transmitter mode -- Master receive mode -- Slave transmitter mode -- Slave receive mode Functional relationships among these operating modes are described below. START AND STOP CONDITIONS When the IIC-bus interface is inactive, it is usually in Slave mode. In other words, the interface should be in Slave mode before detecting a Start condition on the SDA line (a Start condition can be initiated with a High-toLow transition of the SDA line while the clock signal of SCL is High). When the interface state is changed to Master mode, a data transfer on the SDA line can be initiated and SCL signal generated. A Start condition can transfer a one-byte serial data over the SDA line, and a Stop condition can terminate the data transfer. A Stop condition is a Low-to-High transition of the SDA line while SCL is High. Start and Stop conditions are always generated by the master. The IIC-bus gets busy when a Start condition is generated. A Stop condition will make the IIC-bus free. When a master initiates a Start condition, it should send a slave address to notify the slave device. One byte of address field consists of a 7-bit address and a 1-bit transfer direction indicator (showing write or read). If bit 8 is 0, it indicates a write operation (transmit operation); if bit 8 is 1, it indicates a request for data read (receive operation). The master will finish the transfer operation by transmitting a Stop condition. If the master wants to continue the data transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the read-write operation can be performed in various formats. SDA SDA SCL SCL Start Condition Stop Condition Figure 20-2. Start and Stop Condition 20-3 IIC-BUS INTERFACE S3C2410X DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit of the serial data and addresses are always sent first. Write Mode Format with 7-bit Addresses S Slave Address 7bits R/W A "0" (Write) DATA(1Byte) AP Data Transferred (Data + Acknowledge) Write Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "0" (Write) Slave Address 2nd Byte A DATA AP Data Transferred (Data + Acknowledge) Read Mode Format with 7-bit Addresses S Slave Address 7 bits R/W A "1" (Read) DATA AP Data Transferred (Data + Acknowledge) Read Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "1" (Read) Slave Address 2nd Byte A rS Slave Address 1st 7 Bits R/W A "1" (Read) DATA AP Data Transferred (Data + Acknowledge) NOTES: 1. S : Start, rS: Repeat Start, 2. : From Master to Slave, P : Stop, A: Acknowledge : From Slave to Master Figure 20-3. IIC-Bus Interface Data Format 20-4 S3C2410X IIC-BUS INTERFACE SDA MSB Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver SCL S 1 2 7 8 9 ACK 1 2 9 Byte Complete, Interrupt within Receiver Clock Line Held Low by receiver and/or transmitter Figure 20-4. Data Transfer on the IIC-Bus ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master should generate the clock pulse required to transmit the ACK bit. The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received. The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse. The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the ninth clock of SCL is required to complete the one-byte data transfer operation. Clock to Output Data Output by Transmitter Data Output by Receiver SCL from Master S Start Condition 1 2 7 8 9 Clock Pulse for Acknowledgment Figure 20-5. Acknowledge on the IIC-Bus 20-5 IIC-BUS INTERFACE S3C2410X READ-WRITE OPERATION In Transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS) register receives a new data. Before the new data is written into the register, the SCL line will be held low, and then released after it is written. The S3C2410X should hold the interrupt to identify the completion of current data transfer. After the CPU receives the interrupt request, it should write a new data into the IICDS register, again. In Receive mode, when a data is received, the IIC-bus interface will wait until IICDS register is read. Before the new data is read out, the SCL line will be held low and then released after it is read. The S3C2410X should hold the interrupt to identify the completion of the new data reception. After the CPU receives the interrupt request, it should read the data from the IICDS register. BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with a SDA High level detects the other master with a SDA active Low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. The arbitration procedure will be extended until the SDA line turns High. However, when the masters simultaneously lower the SDA line, each master should evaluate whether or not the mastership is allocated to itself. For the purpose of evaluation, each master should detect the address bits. While each master generates the slaver address, it should also detect the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High. Assume that one master generates a Low as first address bit, while the other master is maintaining High. In this case, both masters will detect Low on the bus because the Low status is superior to the High status in power. When this happens, Low (as the first bit of address) generating master will get the mastership while High (as the first bit of address) generating master should withdraw the mastership. If both masters generate Low as the first bit of address, there should be an arbitration for the second address bit, again. This arbitration will continue to the end of last address bit. ABORT CONDITIONS If a slave receiver cannot acknowledge the confirmation of the slave address, it should hold the level of the SDA line High. In this case, the master should generate a Stop condition and to abort the transfer. If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter should then release the SDA to allow a master to generate a Stop condition. CONFIGURING IIC-BUS To control the frequency of the serial clock (SCL), the 4-bit prescaler value can be programmed in the IICCON register. The IIC-bus interface address is stored in the IIC-bus address (IICADD) register. (By default, the IIC-bus interface address has an unknown value.) 20-6 S3C2410X IIC-BUS INTERFACE FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1) Write own slave address on IICADD register, if needed. 2) Set IICCON register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output START Master Tx mode has been configured. Write slave address to IICDS. Write 0xF0 (M/T Start) to IICSTAT. The data of the IICDS is transmitted. ACK period and then interrupt is pending. Stop? N Y Write new data transmitted to IICDS. Write 0xD0 (M/T Stop) to IICSTAT. Clear pending bit to resume. Clear pending bit. The data of the IICDS is shifted to SDA. Wait until the stop condition takes effect. END Figure 20-6. Operations for Master/Transmitter Mode 20-7 IIC-BUS INTERFACE S3C2410X START Master Rx mode has been configured. Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Y Stop? N Read a new data from IICDS. Write 0x90 (M/R Stop) to IICSTAT. Clear pending bit to resume. Clear pending bit. SDA is shifted to IICDS. Wait until the stop condition takes effect. END Figure 20-7. Operations for Master/Receiver Mode 20-8 S3C2410X IIC-BUS INTERFACE START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). N Matched? Y The IIC address match interrupt is generated. Write data to IICDS. Clear pending bit to resume. Y Stop? N The data of the IICDS is shifted to SDA. END Interrupt is pending. Figure 20-8. Operations for Slave/Transmitter Mode 20-9 IIC-BUS INTERFACE S3C2410X START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). N Matched? Y The IIC address match interrupt is generated. Read data to IICDS. Clear pending bit to resume. Y Stop? N SDA is shifted to IICDS. END Interrupt is pending. Figure 20-9. Operations for Slave/Receiver Mode 20-10 S3C2410X IIC-BUS INTERFACE IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register IICCON Address 0x54000000 R/W R/W Description IIC-Bus control register Reset Value 0x0X IICCON Acknowledge generation (note 1) Bit [7] Description IIC-bus acknowledge enable bit. 0 = Disable, 1 = Enable In Tx mode, the IICSDA is free in the ack time. In Rx mode, the IICSDA is L in the ack time. Source clock of IIC-bus transmit clock prescaler selection bit. 0 = IICCLK = fPCLK /16 1 = IICCLK = fPCLK /512 IIC-Bus Tx/Rx interrupt enable/disable bit. 0 = Disable, 1 = Enable IIC-bus Tx/Rx interrupt pending flag. This bit cannot be written to 1. When this bit is read as 1, the IICSCL is tied to L and the IIC is stopped. To resume the operation, clear this bit as 0. 0 = 1) No interrupt pending (when read). 2) Clear pending condition & Resume the operation (when write). 1 = 1) Interrupt is pending (when read) 2) N/A (when write) IIC-Bus transmit clock prescaler. IIC-Bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formula: Tx clock = IICCLK/(IICCON[3:0]+1). Initial State 0 Tx clock source selection Tx/Rx Interrupt (note 5) [6] 0 [5] [4] 0 0 Interrupt pending flag (note 2), (note 3) Transmit clock value (note 4) [3:0] Undefined NOTES: 1. Interfacing with EEPROM, the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode. 2. An IIC-bus interrupt occurs 1) when a 1-byte transmit or receive operation is completed, 2) when a general call or a slave address match occurs, or 3) if bus arbitration fails. 3. To adjust the setup time of IICSDA before IISSCL rising edge, IICDS has to be written before clearing the IIC interrupt pending bit. 4. IICCLK is determined by IICCON[6]. Tx clock can vary by SCL transition time. When IICCON[6]=0, IICCON[3:0]=0x0 or 0x1 is not available. 5. If the IICON[5]=0, IICON[4] does not operate correctly. So, It is recommended that you should set IICCON[5]=1, although you does not use the IIC interrupt. 20-11 IIC-BUS INTERFACE S3C2410X MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register IICSTAT Address 0x54000004 R/W R/W Description IIC-Bus control/status register Reset Value 0x0 IICSTAT Mode selection Bit [7:6] Description IIC-bus master/slave Tx/Rx mode select bits. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode IIC-Bus busy signal status bit. 0 = read) Not busy (when read) write) STOP signal generation 1 = read) Busy (when read) write) START signal generation. The data in IICDS will be transferred automatically just after the start signal. IIC-bus data output enable/disable bit. 0 = Disable Rx/Tx, 1 = Enable Rx/Tx IIC-bus arbitration procedure status flag bit. 0 = Bus arbitration successful 1 = Bus arbitration failed during serial I/O IIC-bus address-as-slave status flag bit. 0 = Cleared when START/STOP condition was detected 1 = Received slave address matches the address value in the IICADD IIC-bus address zero status flag bit. 0 = Cleared when START/STOP condition was detected. 1 = Received slave address is 00000000b. IIC-bus last-received bit status flag bit. 0 = Last-received bit is 0 (ACK was received). 1 = Last-received bit is 1 (ACK was not received). Initial State 00 Busy signal status / START STOP condition [5] 0 Serial output Arbitration status flag Address-as-slave status flag [4] [3] 0 0 [2] 0 Address zero status flag [1] 0 Last-received bit status flag [0] 0 20-12 S3C2410X IIC-BUS INTERFACE MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register IICADD Address 0x54000008 R/W R/W Description IIC-Bus address register Reset Value 0xXX IICADD Slave address Bit [7:0] Description 7-bit slave address, latched from the IIC-bus. When serial output enable = 0 in the IICSTAT, IICADD is writeenabled. The IICADD value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting. Slave address = [7:1] Not mapped = [0] Initial State XXXXXXXX MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT (IICDS) REGISTER Register IICDS Address 0x5400000C R/W R/W Description IIC-Bus transmit/receive data shift register Reset Value 0xXX IICDS Data shift Bit [7:0] Description 8-bit data shift register for IIC-bus Tx/Rx operation. When serial output enable = 1 in the IICSTAT, IICDS is writeenabled. The IICDS value can be read any time, regardless of the current serial output enable bit (IICSTAT) setting. Initial State XXXXXXXX 20-13 IIC-BUS INTERFACE S3C2410X NOTES 20-14 S3C2410X IIS-BUS INTERFACE 21 OVERVIEW IIS-BUS INTERFACE Currently, many digital audio systems are attracting the consumers on the market, in the form of compact discs, digital audio tapes, digital sound processors, and digital TV sound. The S3C2410X Inter-IC Sound (IIS) bus interface can be used to implement a CODEC interface to an external 8/16-bit stereo audio CODEC IC for minidisc and portable applications. The IIS bus interface supports both IIS bus data format and MSB-justified data format. The interface provides DMA transfer mode for FIFO access instead of an interrupt. It can transmit and receive data simultaneously as well as transmit or receive data alternatively at a time. 21-1 IIS-BUS INTERFACE S3C2410X BLOCK DIAGRAM ADDR DATA CNTL BRFC TxFIFO SFTR RxFIFO CHNC SD IPSR_A PCLK IPSR_B SCLKG SCLK LRCK CDCLK Figure 21-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface, register bank, and state machine (BRFC): Bus interface logic and FIFO access are controlled by the state machine. 5-bit dual prescaler (IPSR): One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator. 64-byte FIFOs (TxFIFO and RxFIFO): In transmit data transfer, data are written to TxFIFO, and, in the receive data transfer, data are read from RxFIFO. Master IISCLK generator (SCLKG): In master mode, serial bit clock is generated from the master clock. Channel generator and state machine (CHNC): IISCLK and IISLRCK are generated and controlled by the channel state machine. 16-bit shift register (SFTR): Parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode. TRANSMIT OR RECEIVE ONLY MODE Normal Transfer IIS control register has FIFO ready flag bits for transmit and receive FIFOs. When FIFO is ready to transmit data, the FIFO ready flag is set to '1' if transmit FIFO is not empty. If transmit FIFO is empty, FIFO ready flag is set to '0'. When receive FIFO is not full, the FIFO ready flag for receive FIFO is set to '1' ; it indicates that FIFO is ready to receive data. If receive FIFO is full, FIFO ready flag is set to '0'. These flags can determine the time that CPU is to write or read FIFOs. Serial data can be transmitted or received while the CPU is accessing transmit and receive FIFOs in this way. 21-2 S3C2410X IIS-BUS INTERFACE DMA Transfer In this mode, transmit or receive FIFO is accessible by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. Transmit and Receive Mode In this mode, IIS bus interface can transmit and receive data simultaneously. AUDIO SERIAL INTERFACE FORMAT IIS-BUS FORMAT The IIS bus has four lines including serial data input (IISDI), serial data output (IISDO), left/right channel select (IISLRCK), and serial bit clock (IISCLK); the device generating IISLRCK and IISCLK is the master. Serial data is transmitted in 2's complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. The transmitter does not have to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to '0') for data transmission. If the receiver gets more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver gets fewer bits than its word length, the missing bits are set to zero internally. And therefore, the MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter sends the MSB of the next word at one clock period whenever the IISLRCK is changed. Serial data sent by the transmitter may be synchronized with either the trailing (HIGH to LOW) or the leading (LOW to HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. The LR channel select line indicates the channel being transmitted. IISLRCK may be changed either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The IISLRCK line changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word. MSB (LEFT) JUSTIFIED MSB / left justified bus format is the same as IIS bus format architecturally. Only, different from the IIS bus format, the MSB justified format realizes that the transmitter always sends the MSB of the next word whenever the IISLRCK is changed. 21-3 IIS-BUS INTERFACE S3C2410X LRCK LEFT RIGHT LEFT SCLK MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) SD IIS-bus Format (N=8 or 16) LRCK LEFT RIGHT SCLK MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) SD MSB-justified Format (N=8 or 16) Figure 21-2. IIS-Bus and MSB (Left)-justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (PCLK) can be selected by sampling frequency as shown in Table 21-1. Because PCLK is made by IIS prescaler, the prescaler value and PCLK type (256 or 384fs) should be determined properly. Serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel and PCLK as shown in Table 21-2. Table 21-1. CODEC clock (CODECLK = 256 or 384fs) IISLRCK (fs) 8.000 kHz 256fs CODECLK (MHz) 2.0480 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 11.025 kHz 16.000 kHz 22.050 kHz 32.000 kHz 44.100 kHz 48.000 kHz 64.000 kHz 88.200 kHz 96.000 kHz 21-4 S3C2410X IIS-BUS INTERFACE Table 21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel Serial clock frequency (IISCLK) @CODECLK = 256fs @CODECLK = 384fs 16fs, 32fs 16fs, 32fs, 48fs 32fs 32fs, 48fs 8-bit 16-bit IIS-BUS INTERFACE SPECIAL REGISTERS IIS CONTROL (IISCON) REGISTER Register IISCON Address 0x55000000 (Li/HW, Li/W, Bi/W) 0x55000002 (Bi/HW) R/W R/W Description IIS control register Reset Value 0x100 IISCON Left/Right channel index (Read only) Transmit FIFO ready flag (Read only) Receive FIFO ready flag (Read only) Transmit DMA service request Receive DMA service request Transmit channel idle command Bit [8] [7] [6] [5] [4] [3] 0 = Left 1 = Right 0 = empty 1 = not empty 0 = full 1 = not full 0 = Disable 1 = Enable 0 = Disable 1 = Enable Description Initial State 1 0 0 0 0 0 In Idle state the IISLRCK is inactive (Pause Tx). 0 = Not idle 1 = Idle In Idle state the IISLRCK is inactive (Pause Rx). 0 = Not idle 1 = Idle 0 = Disable 1 = Enable 0 = Disable (stop) 1 = Enable (start) Receive channel idle command [2] 0 IIS prescaler IIS interface [1] [0] 0 0 NOTES: 1. The IISCON register is accessible for each byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Little/HalfWord/Word (Bi/HW/W): Big/HalfWord/Word 21-5 IIS-BUS INTERFACE S3C2410X IIS MODE REGISTER (IISMOD) REGISTER Register IISMOD Address 0x55000004 (Li/W, Li/HW, Bi/W) 0x55000006 (Bi/HW) R/W R/W Description IIS mode register Reset Value 0x0 IISMOD Master/slave mode select Bit [8] Description 0 = Master mode (IISLRCK and IISCLK are output mode). 1 = Slave mode (IISLRCK and IISCLK are input mode). 00 = No transfer 01 = Receive mode 10 = Transmit mode 11 = Transmit and receive mode 0 = Low for left channel (High for right channel) 1 = High for left channel (Low for right channel) 0 = IIS compatible format 1 = MSB (Left)-justified format 0 = 8-bit 1 = 16-bit 0 = 256fs 1 = 384fs (fs: sampling frequency) 00 = 16fs 01 = 32fs 10 = 48fs 11 = N/A Initial State 0 Transmit/receive mode select [7:6] 00 Active level of left/right channel Serial interface format Serial data bit per channel Master clock frequency select [5] [4] [3] [2] 0 0 0 0 Serial bit clock frequency select [1:0] 00 NOTES: 1. The IISMOD register is accessible for each halfword and wordunit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Little/HalfWord/Word. (Bi/HW/W): Big/HalfWord/Word. 21-6 S3C2410X IIS-BUS INTERFACE IIS PRESCALER (IISPSR) REGISTER Register IISPSR Address 0x55000008 (Li/HW, Li/W, Bi/W) 0x5500000A (Bi/HW) R/W R/W Description IIS prescaler register Reset Value 0x0 IISPSR Prescaler control A Bit [9:5] Description Data value: 0 ~ 31 Note: Prescaler A makes the master clock that is used the internal block and division factor is N+1. Data value: 0 ~ 31 Note: Prescaler B makes the master clock that is used the external block and division factor is N+1. Initial State 00000 Prescaler control B [4:0] 00000 NOTES: 1. The IISPSR register is accessible for each byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR instructions or char/short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W) : Little/HalfWord/Word. (Bi/HW/W) : Big/HalfWord/Word. 21-7 IIS-BUS INTERFACE S3C2410X IIS FIFO CONTROL (IISFCON) REGISTER Register IISFCON Address 0x5500000C (Li/HW, Li/W, Bi/W) 0x5500000E (Bi/HW) R/W R/W Description IIS FIFO interface register Reset Value 0x0 IISFCON Transmit FIFO access mode select Receive FIFO access mode select Transmit FIFO Receive FIFO Transmit FIFO data count (Read only) Receive FIFO data count (Read only) Bit [15] [14] [13] [12] [11:6] [5:0] 0 = Normal 1 = DMA 0 = Normal 1 = DMA 0 = Disable 0 = Disable Description Initial State 0 0 1 = Enable 1 = Enable 0 0 000000 000000 Data count value = 0 ~ 32 Data count value = 0 ~ 32 NOTES: 1. The IISFCON register is accessible for each halfword and word unit using STRH/STR and LDRH/LDR instructions or short int/int type pointer in Little/Big endian mode. 2. (Li/HW/W): Little/HalfWord/Word. (Bi/HW/W): Big/HalfWord/Word. IIS FIFO (IISFIFO) REGISTER IIS bus interface contains two 64-byte FIFO for the transmit and receive mode. Each FIFO has 16-width and 32depth form, which allows the FIFO to handles data for each halfword unit regardless of valid data size. Transmit and receive FIFO access is performed through FIFO entry; the address of FENTRY is 0x55000010. Register IISFIFO Address 0x55000010(Li/HW) 0x55000012(Bi/HW) R/W R/W Description IIS FIFO register Reset Value 0x0 IISFIF FENTRY Bit [15:0] Description Transmit/Receive data for IIS Initial State 0x0 NOTES: 1. The IISFIFO register is accessible for each halfword and word unit using STRH and LDRH instructions or short int type pointer in Little/Big endian mode. 2. (Li/HW): Little/HalfWord. (Bi/HW): Big/HalfWord. 21-8 S3C2410X SPI INTERFACE 22 OVERVIEW FEATURES SPI INTERFACE The S3C2410X Serial Peripheral Interface (SPI) can interface the serial data transfer. The S3C2410X includes two SPI, each of which has two 8-bit shift registers for transmission and receiving, respectively. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). 8-bit serial data at a frequency is determined by its corresponding control register settings. If you only want to transmit, received data can be dummy. Otherwise, if you only want to receive, you should transmit dummy '1' data. There are 4 I/O pin signals associated with SPI transfers: the SCK (SPICLK0,1), the MISO (SPIMISO0,1) data line, the MOSI (SPIMOSI0,1) data line, and the active low /SS (nSS0,1) pin (input). -- SPI Protocol (ver. 2.11) compatible -- 8-bit Shift Register for transmit -- 8-bit Shift Register for receive -- 8-bit Prescaler logic -- Polling, Interrupt, and DMA transfer mode 22-1 SPI INTERFACE S3C2410X BLOCK DIAGRAM LSB 8 Data Bus 8 MSB Slave Master Slave Master Pin Control Logic 0 SPIMISO 0 MISO SPIMOSI 0 MOSI Tx 8bit Shift Reg 0 MSB LSB Rx 8bit Shift Reg 0 PCLK 8bit Prescaler 0 SPI Clock (Master) CPOL CPHA Clock CLOCK Logic 0 Slave Master SPICLK 0 SCK Prescaler Register 0 nSS 0 Status Register 0 Slave REDY DCOL MULF /SS INT 0 / INT 1 REQ0 / REQ1 ACK0 / ACK1 APB I/F 0 (INT DMA 0) MSTR LSB 8 MSB Slave Master Slave Master Pin Control Logic 1 SPIMISO 1 MISO SPIMOSI 1 MOSI Tx 8bit Shift Reg 1 MSB 8 Rx 8bit Shift Reg 1 LSB PCLK 8bit Prescaler 1 SPI Clock (Master) CPOL CPHA Clock CLOCK Logic 1 Slave Master SPICLK 1 SCK Prescaler Register 1 nSS 1 Status Register 1 Slave DCOL REDY MULF /SS INT 0 / INT 1 REQ0 / REQ1 ACK0 / ACK1 APB I/F 1 (INT DMA 1) MSTR Figure 22-1. SPI Block Diagram 22-2 S3C2410X SPI INTERFACE SPI OPERATION Using the SPI interface, the S3C2410X can send/receive 8 -bit data simultaneously with an external device. A serial clock line is synchronized with the two data lines for shifting and sampling of the information. When the SPI is the master, transmission frequency can be controlled by setting the appropriate bit to SPPREn register. You can modify its frequency to adjust the baud rate data register value. When the SPI is a slave, other master supplies the clock. When the programmer writes byte data to SPTDATn register, SPI transmit/receive operation will start simultaneously. In some cases, nSS should be activated before writing byte data to SPTDATn. Programming Procedure When a byte data is written into the SPTDATn register, SPI starts to transmit if ENSCK and MSTR of SPCONn register are set. You can use a typical programming procedure to operate an SPI card. To program the SPI modules, follow these basic steps: 1. Set Baud Rate Prescaler Register (SPPREn). 2. Set SPCONn to configure properly the SPI module. 3. Write data 0xFF to SPTDATn 10 times in order to initialize MMC or SD card. 4. Set a GPIO pin, which acts as nSS, to low to activate the MMC or SD card. 5. Tx data Check the status of Transfer Ready flag (REDY=1), and then write data to SPTDATn. 6. Rx data(1): SPCONn's TAGD bit disable = normal mode write 0xFF to SPTDATn, then confirm REDY to set, and then read data from Read Buffer. 7. Rx data(2): SPCONn's TAGD bit enable = Tx Auto Garbage Data mode confirm REDY to set, and then read data from Read Buffer(then automatically start to transfer). 8. Set a GPIO pin, which acts as nSS, to high, to deactivate MMC or SD card. 22-3 SPI INTERFACE S3C2410X SPI Transfer Format The S3C2410X supports 4 different format to transfer the data. Figure 22-2 shows four waveforms for SPICLK.. CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB* 1 2 3 4 5 6 7 8 * MSB of character just received CPOL = 0, CPHA = 1 (Format B) Cycle SPICLK MOSI MISO *LSB MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB* 1 2 3 4 5 6 7 8 * LSB of previously transmitted character CPOL = 1, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB* 1 2 3 4 5 6 7 8 * MSB of character just received CPOL = 1, CPHA = 1 (Format B) Cycle SPICLK MOSI MISO MSB *LSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB 1 2 3 4 5 6 7 8 * LSB of previously transmitted character Figure 22-2. SPI Transfer Format 22-4 S3C2410X SPI INTERFACE Transmitting Procedure by DMA 1. The SPI is configured as DMA mode. 2. DMA is configured properly. 3. The SPI requests DMA service. 4. DMA transmits 1byte data to the SPI. 5. The SPI transmits the data to card. 6. Return to Step 3 until DMA count becomes 0. 7. The SPI is configured as interrupt or polling mode with SMOD bits. Receiving Procedure by DMA 1. The SPI is configured as DMA start with SMOD bits and setting TAGD bit. 2. DMA is configured properly. 3. The SPI receives 1byte data from card. 4. The SPI requests DMA service. 5. DMA receives the data from the SPI. 6. Write data 0xFF automatically to SPTDATn. 7. Return to Step 4 until DMA count becomes 0. 8. The SPI is configured as polling mode with SMOD bits and clearing TAGD bit. 9. If SPSTAn's REDY flag is set, then read the last byte data. NOTE: Total received data = DMA TC values + the last data in polling mode (Step 9). The first DMA received data is dummy and so the user can neglect it. SPI Slave Rx Mode with Format B If the SPI slave Rx mode is activated and SPI format is set to format B, then SPI operation will be failed: The READY signal, one of internal signals, becomes high before the SPI_CNT reaches 0. Therefore, in DMA mode, DATA_READ signal is generated before the last data is latched. 22-5 SPI INTERFACE S3C2410X Guide 1) DMA mode: This mode cannot be used at SPI slave Rx mode with format B. 2) Polling mode: DATA_READ signal should be delayed by 1phase of SPICLK at SPI slave Rx mode with format B. 3) Interrupt mode: DATA_READ signal should be delayed 1phase of SPICLK at SPI slave Rx mode with format B. SPI Data Receive Function Error (Slave/Receive/Format B Mode) SPI_CNT Value 7 SPICLK Data Latch READY (Internal) Data Read DATA_READ (Internal) 6 5 4 3 2 1 0 22-6 S3C2410X SPI INTERFACE SPI SPECIAL REGISTERS SPI CONTROL REGISTER Register SPCON0 SPCON1 Address 0x59000000 0x59000020 R/W R/W R/W Description SPI channel 0 control register SPI channel 1 control register Reset Value 0x00 0x00 SPCONn SPI Mode Select (SMOD) SCK Enable (ENSCK) Bit [6:5] Description Determine how and by what SPTDAT is read/written. 00 = polling mode, 01 = interrupt mode 10 = DMA mode, 11 = reserved Determine whether you want SCK enable or not (for only master). 0 = disable, 1 = enable Determine the desired mode (master or slave). 0 = slave, 1 = master NOTE: In slave mode, there should be set up time for master to initiate Tx/Rx. Determine an active high or active low clock. 0 = active high, 1 = active low Select one of two fundamentally different transfer formats. 0 = format A, 1 = format B Decide whether the receiving data only needs or not. 0 = normal mode, 1 = Tx auto garbage data mode NOTE: In normal mode, if you only want to receive data, you should transmit dummy 0xFF data. Initial State 00 [4] 0 Master/Slave Select (MSTR) [3] 0 Clock Polarity Select (CPOL) Clock Phase Select (CPHA) Tx Auto Garbage Data mode enable (TAGD) [2] [1] [0] 0 0 0 22-7 SPI INTERFACE S3C2410X SPI STATUS REGISTER Register SPSTA0 SPSTA1 Address 0x59000004 0x59000024 R/W R R Description SPI channel 0 status register SPI channel 1 status register Reset Value 0x01 0x01 SPSTAn Reserved Data Collision Error Flag (DCOL) Bit [7:3] [2] Description This flag is set if the SPTDATn is written or the SPRDATn is read while a transfer is in progress and cleared by reading the SPSTAn. 0 = not detect, 1 = collision error detect This flag is set if the nSS signal goes to active low while the SPI is configured as a master, and SPPINn's ENMUL bit is multi master errors detect mode. MULF is cleared by reading SPSTAn. 0 = not detect, 1 = multi master error detect This bit indicates that SPTDATn or SPRDATn is ready to transmit or receive. This flag is automatically cleared by writing data to SPTDATn. 0 = not ready, 1 = data Tx/Rx ready Initial State 0 Multi Master Error Flag (MULF) [1] 0 Transfer Ready Flag (REDY) [0] 1 22-8 S3C2410X SPI INTERFACE SPI PIN CONTROL REGISTER When the SPI system is enabled, the direction of pins, except nSS pin, is controlled by MSTR bit of SPCONn register. The direction of nSS pin is always input. When the SPI is a master, nSS pin is used to check multi-master error, provided the SPPIN's ENMUL bit is active, and another GPIO should be used to select a slave. If the SPI is configured as a slave, the nSS pin is used to select SPI as a slave by one master. Register SPPIN0 SPPIN1 Address 0x59000008 0x59000028 R/W R/W R/W Description SPI channel 0 pin control register SPI channel 1 pin control register Reset Value 0x02 0x02 SPPINn Reserved Multi Master error detect Enable (ENMUL) Bit [7:3] [2] Description The /SS pin is used as an input to detect multi master error when the SPI system is a master. 0 = disable (general purpose) 1 = multi master error detect enable This bit should be `1'. Determine MOSI drive or release when 1byte transmit is completed (only master). 0 = release, 1 = drive the previous level Initial State 0 Reserved Master Out Keep (KEEP) [1] [0] 1 0 The SPIMISO (MISO) and SPIMOSI (MOSI) data pins are used for transmitting and receiving serial data. When the SPI is configured as a master, SPIMISO (MISO) is the master data input line, SPIMOSI (MOSI) is the master data output line, and SPICLK (SCK) is the clock output line. When the SPI becomes a slave, these pins perform reversed roles. In a multiple-master system, SPICLK (SCK) pins, SPIMOSI (MOSI) pins, and SPIMISO (MISO) pins are tied to configure a group respectively. A master SPI can experience a multi master error, when other SPI device working as a master selects the S3C2410 SPI as a slave. When this error is detected, the following actions are taken immediately. But you must previously set SPPINn's ENMUL bit if you want to detect this error. 1. The SPCONn's MSTR bit is forced to 0 to operate slave mode. 2. The SPSTAn's MULF flag is set, and an SPI interrupt is generated. 22-9 SPI INTERFACE S3C2410X SPI Baud Rate Prescaler Register Register SPPRE0 SPPRE1 Address 0x5900000C 0x5900002C R/W R/W R/W Description SPI cannel 0 baud rate prescaler register SPI cannel 1 baud rate prescaler register Reset Value 0x00 0x00 SPPREn Prescaler Value Bit [7:0] Description Determine SPI clock rate as above equation. Baud rate = PCLK / 2 / (Prescaler value + 1) Initial State 0x00 NOTE: Baud rate should be less than 25 MHz. SPI Tx Data Register Register SPTDAT0 SPTDAT1 Address 0x59000010 0x59000030 R/W R/W R/W Description SPI channel 0 Tx data register SPI channel 1 Tx data register Reset Value 0x00 0x00 SPTDATn Tx Data Register Bit [7:0] Description This field contains the data to be transmitted over the SPI channel. Initial State 0x00 SPI Rx Data Register Register SPRDAT0 SPRDAT1 Address 0x59000014 0x59000034 R/W R R Description SPI channel 0 Rx data register SPI channel 1 Rx data register Reset Value 0x00 0x00 SPRDATn Rx Data Register Bit [7:0] Description This field contains the data to be received over the SPI channel. Initial State 0x00 22-10 S3C2410X BUS PRIORITIES 23 OVERVIEW BUS PRIORITY MAP BUS PRIORITIES The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode. The S3C2410X holds eleven bus masters including SDRAM refresh controller, LCD_DMA, DMA0, DMA1, DMA2, DMA3, USB_HOST_DMA, EXT_BUS_MASTER, Test interface controller (TIC), and ARM920T. The following list shows the priorities among these bus masters after a reset: 1. SDRAM refresh controller 2. LCD_DMA 3. DMA0 4. DMA1 5. DMA2 6. DMA3 7. USB host DMA 8. External bus master 9. TIC 10. ARM920T 11. Reserved Among those bus masters, four DMAs operate under the rotation priority, while others run under the fixed priority. 23-1 BUS PRIORITIES S3C2410X NOTES 23-2 S3C2410X ELECTRICAL DATA 24 Parameter DC Supply Voltage DC Input Voltage DC Output Voltage ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 24-1. Absolute Maximum Rating Symbol VDDi VDDIO VIN VOUT IIN TSTG 1.8V VDD 3.3V VDD 3.3V Input buffer 3.3V Interface / 5V Tolerant input buffer 3.3V Output buffer 200 - 65 to 150 Rating 2.7 3.8 3.8 6.5 3.8 mA o Unit V DC Input (Latch-up) Current Storage Temperature C RECOMMENDED OPERATING CONDITIONS Table 24-2. Recommended Operating Conditions Parameter DC Supply Voltage for Internal DC Supply Voltage for I/O Block DC Supply Voltage for Analog Core DC Input Voltage Symbol VDDi VDDIO VDD VIN VOUT TOPR 1.8V VDD 3.3V VDD 3.3V VDD 3.3V Input buffer 3.3V Interface / 5V Tolerant input buffer DC Output Voltage Operating Temperature 3.3V Output buffer Commercial Rating 1.8 0.15 3.3 0.3 3.3 5% 3.3 0.3 3.0 - 5.25 3.3 0.3 0 to 70 o Unit V C 24-1 ELECTRICAL DATA S3C2410X D.C. ELECTRICAL CHARACTERISTICS Table 24-3 and 24-4 define the DC electrical characteristics for the standard LVCMOS I/O buffers. Table 24-3. Normal I/O PAD DC Electrical Characteristics (VDD = 3.3V 0.3V, TA = 0 to 70 C) Symbol VIH VIL VT VT+ VTIIH Parameters High level input voltage LVCMOS interface Low level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer IIL Low level input current Input buffer Input buffer with pull-up VOH High level output voltage Type B6 Type B8 Type B12 VOL Low level output voltage Type B6 Type B8 Type B12 NOTES: 1. Type B6 means 6mA output driver cell. 2. Type B8 means 8mA output driver cell. 3. Type B12 means 12mA output driver cells. Condition Min Type Max Unit 2.0 V 0.8 1.4 CMOS CMOS 0.8 2.0 V V V V A A VIN = VDD -10 10 VIN = VSS -10 -60 -33 10 -10 IOH= - 6 mA IOH= - 8 mA IOH = -12 mA 2.4 V IOL = 6 mA IOL = 8 mA IOL = 12 mA 0.4 V 24-2 S3C2410X ELECTRICAL DATA Table 24-4. USB DC Electrical Characteristics Symbol VIH VIL IIH IIL VOH VOL Parameter High level input voltage Low level input voltage High level input current Low level input current Static Output High Static Output Low Vin = 3.3V Vin = 0.0V 15K to GND 1.5K to 3.6V -10 -10 2.8 Condition Min 2.5 0.8 10 10 3.6 0.3 Max Unit V V A A V V Table 24-5. S3C2410X Power Supply Voltage and Current Parameter Typical VDDi / VDDIO Max. Operating frequency (FCLK) Max. Operating frequency (HCLK) Max. Operating frequency (PCLK) Typical normal mode power NOTE(3) (Total VDDi + VDDIO) Typical normal mode power NOTE(3) (Total VDDi + VDDIO) Typical idle mode power NOTE(3) (Total VDDi + VDDIO) Typical slow mode power NOTE(3) (Total VDDi + VDDIO) Maximum Power_OFF mode power Typical Power_OFF mode power NOTE(3) Maximum RTC power Typical RTC power NOTE(3) 80 8 63 3 uA uA uA uA 33 mW 122 mW FCLK = 203MHz (F:H:P = 1:2:4) FCLK = 12MHz (F:H:P = 1:1:1) @1.95V/3.6V, Room temperature All other I/O static. @1.95V/3.6V, Room temperature X-tal = 32.768KHz for RTC 224 mW NOTE(2) Value 1.8 / 3.3 203 101.5 50.7 297 Unit V MHz MHz MHz mW Condition NOTE(1) NOTES: 1. I/D cache: ON, MMU: ON, Code on SRAM, FCLK:HCLK:PCLK = 203MHz:101.5MHz:50.7MHz :LCD ON (320x240x16bppx60Hz, color TFT):Timer internal mode(5 Channel run) :Audio(IIS&DMA,CDCLK=16.9MHz,LRCK=44.1KHz):Integer data quick sort(65536 EA) 2. WinCE 3.0 MPEG play. 3. Room temperature specification. 24-3 ELECTRICAL DATA S3C2410X Table 24-6. Typical Current Decrease by CLKCON Register (FCLK@202.8MHz) (Unit: mA) Peripherals NFC Current 2.9 LCD 5.8 USBH 0.4 USBD 2.9 Timer 0.5 SDI 1.9 UART 3.6 RTC 0.4 ADC 0.4 IIC 0.6 IIS 0.5 SPI 0.5 Total 20.4 NOTE: This table includes each power consumption of each peripherals. For example, If you do not use IIS and you turned off IIS block by CLKCON register, you can save the 0.5mA . FCLK(MHz) 280 266 260 250 237 220 203 100 50 10 Spec. Guaranteed Area 1.5 1.6 1.65 1.7 1.8 1.9 1.95 2.0 2.1 VDDCPU(V) Figure 24-1. Typical Operating Voltage/Frequency Range (VDDIO=3.3V, @Room temperature & SMDK2410 board) 24-4 S3C2410X ELECTRICAL DATA A.C. ELECTRICAL CHARACTERISTICS tXTALCYC 1/2 VDD 1/2 VDD NOTE: The clock input from the XTIpll pin. Figure 24-2. XTIpll Clock Timing tEXTCYC tEXTHIGH tEXTLOW 1/2 VDD VIH VIH VIL VIL VIH 1/2 VDD NOTE: The clock input from the EXTCLK pin. Figure 24-3. EXTCLK Clock Input Timing EXTCLK tEX2HC HCLK (internal) Figure 24-4. EXTCLK/HCLK in case that EXTCLK is used without the PLL 24-5 ELECTRICAL DATA S3C2410X HCLK (internal) tHC2CK CLKOUT (HCLK) tHC2SCLK SCLK Figure 24-5. HCLK/CLKOUT/SCLK in case that EXTCLK is used EXTCLK nRESET tRESW Figure 24-6. Manual Reset Input Timing 24-6 S3C2410X ELECTRICAL DATA Power PLL can operate after OM[3:2] is latched. nRESET XTIpll or EXTCLK ... PLL is configured by S/W first time. tPLL VCO is adapted to new clock frequency. Clock Disable VCO output ... tRST2RUN ... FCLK MCU operates by XTIpll or EXTCLK clcok. FCLK is new frequency. Figure 24-7. Power-On Oscillation Setting Timing 24-7 ELECTRICAL DATA S3C2410X EXTCLK XTIpll Clock Disable tOSC2 VCO Output Several slow clocks (XTIpll or EXTCLK) FCLK Power_OFF mode is initiated. Figure 24-8. Power_OFF Mode Return Oscillation Setting Timing 24-8 S3C2410X HCLK tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD ADDR tRCD tRCD nGCSx tROD tROD nOE Tacc nBEx '1' tRDS tRDS tRDS tRDS tRDS tRDS tRDS tRDS DATA tRDH tRDH tRDH tRDH tRDH tRDH tRDH tRDH Figure 24-9. ROM/SRAM Burst READ Timing(I) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit) ELECTRICAL DATA 24-9 24-10 ELECTRICAL DATA HCLK tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD ADDR tRCD tRCD nGCSx tROD tROD nOE Tacc tRBED tRBED nBEx tRDS tRDS tRDS tRDS tRDS tRDS tRDS tRDS DATA tRDH tRDH tRDH tRDH tRDH tRDH tRDH tRDH Figure 24-10. ROM/SRAM Burst READ Timing(II) (Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit) S3C2410X S3C2410X ELECTRICAL DATA HCLK tHZD ADDR 'HZ' tHZD nGS 'HZ' tHZD nOE 'HZ' tXnBRQS XnBREQ tXnBACKD XnBACK tXnBACKD tXnBRQH Figure 24-11. External Bus Request in ROM/SRAM Cycle (Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0) 24-11 ELECTRICAL DATA S3C2410X HCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tROD Tcah tRCD tRAD Tcos Tacc Toch nWBEx '1' tRDS DATA tRDH Figure 24-12. ROM/SRAM READ Timing (I) (Tacs=2,Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0) 24-12 S3C2410X ELECTRICAL DATA HCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tROD Tcah tRCD tRAD Tcos Tacc tRBED Toch tRBED nBEx tRDS DATA tRDH Figure 24-13. ROM/SRAM READ Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1) 24-13 ELECTRICAL DATA S3C2410X HCLK tRAD ADDR tRCD nGCSx Tacs Tcah tRWD nWE tRWD tRCD tRAD Tcos Tacc tRWBED Toch tRWBED nWBEx Tcos Toch tRDD tRDD DATA Figure 24-14. ROM/SRAM WRITE Timing (I) (Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0 24-14 S3C2410X ELECTRICAL DATA HCLK tRAD ADDR tRCD nGCSx Tacs Tcah tRWD nWE tRWD tRCD tRAD Tcos Tacc tRBED Toch tRBED nBEx tRDD DATA tRDD Figure 24-15. ROM/SRAM WRITE Timing (II) (Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1) 24-15 ELECTRICAL DATA S3C2410X HCLK tRC ADDR nGCSx Tacs delayed nOE Tacs sampling nWait nWait Tacc = 6cycle DATA NOTE: The status of nWait is checked at (Tacc-1) cycle. Figure 24-16. External nWAIT READ Timing (Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0) HCLK ADDR nGCSx nWE Tacc >= 2cycle tWH tWS nWait tRDD DATA tRDD Figure 24-17. External nWAIT WRITE Timing (Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0) 24-16 S3C2410X ELECTRICAL DATA HCLK tRAD ADDR tRCD nGCSx Tacs tROD nOE tRAD Tcos Tacc tRDS DATA tRDH Figure 24-18. Masked-ROM Single READ Timing (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11) HCLK tRAD ADDR tRCD nGCSx tRAD tRAD tRAD tRAD tRAD tROD nOE Tacc Tpac tRDS DATA tRDH tRDH tRDH tRDH tRDH Tpac tRDS tRDS Tpac Tpac tRDS tRDS Figure 24-19. Masked-ROM Consecutive READ Timing (Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11) 24-17 ELECTRICAL DATA S3C2410X tSCSD Trp Trcd tSBED tSCD Tcl '1' tSAD ADDR/BA tSAD A10/AP tSRD nSRAS nSCAS nGCSx SCKE tSWD tSDS Figure 24-20. SDRAM Single Burst READ Timing (Trp=2, Trcd=2, Tcl=2, DW=16bit) 24-18 DATA SCLK nBEx nWE tSDH S3C2410X ELECTRICAL DATA EXTCLK tHZD SCLK 'HZ' tHZD SCKE '1' tHZD 'HZ' ADDR/BA 'HZ' tHZD A10/AP tHZD 'HZ' nGCSx tHZD 'HZ' nSRAS tHZD 'HZ' nSCAS tHZD 'HZ' nBEx tHZD 'HZ' nWE 'HZ' tXnBRQS XnBREQ tXnBRQL tXnBRQH XnBACK tXnBACKD tXnBACKD Figure 24-21. External Bus Request in SDRAM Timing (Trp=2, Trcd=2, Tcl=2) 24-19 ELECTRICAL DATA S3C2410X SCLK SCKE '1' tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSRD nSRAS tSRD tSCD nSCAS nBEx '1' tSWD nWE tSWD DATA 'HZ' Figure 24-22. SDRAM MRS Timing 24-20 S3C2410X ELECTRICAL DATA SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD tSRD nSRAS Trp tSRD Trcd tSCD nSCAS tSBED nBEx Tcl tSWD nWE tSDS DATA tSDH Figure 24-23. SDRAM Single READ Timing(I) (Trp=2, Trcd=2, Tcl=2) 24-21 ELECTRICAL DATA S3C2410X SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD tSRD nSRAS Trp tSRD Trcd tSCD nSCAS tSBED nBEx Tcl tSWD nWE tSDS DATA tSDH Figure 24-24. SDRAM Single READ Timing(II) (Trp=2, Trcd=2, Tcl=3) 24-22 S3C2410X ELECTRICAL DATA SCLK SCKE '1' tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSRD nSRAS Trp tSRD '1' Trc tSCD nSCAS nBEx '1' tSWD nWE DATA 'HZ' NOTE: Before executing auto/self refresh command, all banks must be in idle state. Figure 24-25. SDRAM Auto Refresh Timing (Trp=2, Trc=4) 24-23 24-24 tSCSD tSRD Trp Trcd tSCD tSBED Tcl tSWD Tcl Tcl tSDS tSDH SCLK ELECTRICAL DATA SCKE '1' tSAD ADDR/BA tSAD A10/AP nGCSx nSRAS nSCAS nBEx Figure 24-26. SDRAM Page Hit-Miss READ Timing (Trp=2, Trcd=2, Tcl=2) nWE DATA S3C2410X S3C2410X ELECTRICAL DATA SCLK tCKED SCKE tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD '1' tSAD tCKED tSRD nSRAS Trp tSRD '1' Trc '1' tSCD nSCAS '1' nBEx '1' '1' tSWD nWE '1' DATA 'HZ' 'HZ' NOTE: Before executing auto/self refresh command, all banks must be in idle state. Figure 24-27. SDRAM Self Refresh Timing (Trp=2, Trc=4) 24-25 ELECTRICAL DATA S3C2410X SCLK SCKE '1' tSAD tSAD tSAD tSAD ADDR/BA tSAD A10/AP tSCSD nGCSx tSCSD tSCSD tSAD tSRD nSRAS Trp tSRD Trcd tSCD nSCAS tSBED nBEx tSWD nWE tSDD DATA tSDD Figure 24-28. SDRAM Single Write Timing (Trp=2, Trcd=2) 24-26 S3C2410X ELECTRICAL DATA tSBED tSCD tSCSD Trp Trcd '1' tSAD ADDR/BA tSAD A10/AP tSRD nSRAS nSCAS nGCSx SCKE tSWD tSDD Figure 24-29. SDRAM Page Hit-Miss Write Timing (Trp=2, Trcd=2, Tcl=2) DATA SCLK nBEx nWE tSDD 24-27 ELECTRICAL DATA S3C2410X XSCLK tXRS XnXDREQ tXAD XnXDACK Min. 3SCLK tCADL Read Write tXRS tCADH Figure 24-30. External DMA Timing (Handshake, Single transfer) Tf2hsetup VSYNC Tf2hhold HSYNC Tvfpd Tvspw VDEN Tvbpd HSYNC Tl2csetup VCLK Tvclkl VD Tvdsetup VDEN Tle2chold LEND Tlewidth Tve2hold Tvdhold Tvclkh Tvclk Figure 24-31. TFT LCD Controller Timing 24-28 S3C2410X ELECTRICAL DATA IISSCLK tLRCK IISLRCK (out) tSDO IISLRCK (out) tSDIS IISSDI (in) tSDIH Figure 24-32. IIS Interface Timing fSCL tSCLHIGH tSCLLOW IICSCL tSTOPH tBUF tSTARTS tSDAS tSDAH IICSDA Figure 24-33. IIC Interface Timing 24-29 ELECTRICAL DATA S3C2410X SDCLK tSDCD SDCMD (out) tSDCS SDCMD (in) tSDCH tSDDD SDDATA[3:0] (out) tSDDS SDDATA[3:0] (in) tSDDH Figure 24-34. SD/MMC Interface Timing SPICLK tSPIMOD SPIMOSI (MO) tSPISIS SPIMOSI (SI) tSPISIH tSPISOD SPIMISO (SO) tSPIMIS SPIMISO (MI) tSPIMIH Figure 24-35. SPI Interface Timing (CPHA=1, CPOL=1) 24-30 S3C2410X ELECTRICAL DATA TACLS TWRPH0 TWRPH1 TACLS TWRPH0 TWRPH1 HCLK HCLK tCLED CLE tWED nFWE tCLED ALE tALED tALED tWED nFWE tWED tWED tWDS DATA[7:0] COMMAND tWDH DATA[7:0] tWDS ADDRESS tWDH Figure 24-36. NAND Flash Address/Command Timing TWRPH0 TWRPH1 TWRPH0 TWRPH1 HCLK tWED tWED nFWE tWDS DATA[7:0] WDATA HCLK tWED nFRE tWED tWDH DATA[7:0] RDATA tRDS tRDH Figure 24-37. NAND Flash Timing 24-31 ELECTRICAL DATA S3C2410X Table 24-7. Clock Timing Constants (VDDi, VDDalive, VDDiarm = 1.8 V 0.15 V, TA = 0 to 70 C, VDDMOP = 3.3V 0.3V) Parameter Crystal clock input frequency Crystal clock input cycle time External clock input frequency External clock input cycle time External clock input low level pulse width External clock to HCLK (without PLL) HCLK (internal) to CLKOUT HCLK (internal) to SCLK External clock input high level pulse width Reset assert time after clock stabilization PLL Lock Time Power_OFF mode return oscillation setting time The interval before CPU runs after nRESET is released. Symbol f XTAL tXTALCYC f EXT tEXTCYC tEXTLOW tEX2HC tHC2CK tHC2SCLK tEXTHIGH tRESW tPLL tOSC2 tRST2RUN Min 10 50 - 15.0 7 3 3 0 4 4 200 - - Typ - - - - - - - - - - - - 7 65536 - Max 20 100 66 - - 9 11 3 - - Unit MHz ns MHz ns ns ns ns ns ns XTIpll or EXTCLK uS XTIpll or EXTCLK XTIpll or EXTCLK 24-32 S3C2410X ELECTRICAL DATA Table 24-8. ROM/SRAM Bus Timing Constants (VDDi, VDDalive, VDDiarm = 1.8 V 0.15 V, TA = 0 to 70 C, VDDMOP = 3.3V 0.3V) Parameter ROM/SRAM Address Delay ROM/SRAM Chip select Delay ROM/SRAM Output enable Delay ROM/SRAM read Data Setup time. ROM/SRAM read Data Hold time. ROM/SRAM Byte Enable Delay ROM/SRAM Write Byte Enable Delay ROM/SRAM output Data Delay ROM/SRAM external Wait Setup time ROM/SRAM external Wait Hold time ROM/SRAM Write enable Delay Symbol tRAD tRCD tROD tRDS tRDH tRBED tRWBED tRDD tWS tWH tRWD Min 3 2 2 4 0 2 2 3 5 0 2 Typ - - - - - - - - - - - Max 11 9 8 - - 8 10 12 - - 9 Unit ns ns ns ns ns ns ns ns ns ns ns Table 24-9. Memory Interface Timing Constants (3.3V) (VDDi, VDDalive, VDDiarm = 1.8 V 0.15 V, TA = 0 to 70 C, VDDMOP = 3.3V 0.3V) Parameter SDRAM Address Delay SDRAM Chip Select Delay SDRAM Row active Delay SDRAM Column active Delay SDRAM Byte Enable Delay SDRAM Write enable Delay SDRAM read Data Setup time SDRAM read Data Hold time SDRAM output Data Delay SDRAM Clock Enable Delay Symbol tSAD tSCSD tSRD tSCD tSBED tSWD tSDS tSDH tSDD Tcked Min 2 2 1 1 2 2 4 0 2 2 Typ - - - - - - - - - - Max 7 6 5 5 6 6 - - 7 5 Unit ns ns ns ns ns ns ns ns ns ns 24-33 ELECTRICAL DATA S3C2410X Table 24-10. External Bus Request Timing Constants (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter eXternal Bus Request Setup time eXternal Bus Request Hold time eXternal Bus Ack Delay HZ Delay Symbol tXnBRQS tXnBRQH tXnBACKD tHZD Min 2 - 9 4 Typ. - - - - Max 5 1 11 12 Unit ns ns ns ns Table 24-11. DMA Controller Module Signal Timing Constants (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter eXternal Request Setup aCcess to Ack Delay when Low transition aCcess to Ack Delay when High transition eXternal Request Delay Symbol tXRS tCADL tCADH tXAD Min 2 9 9 2 Typ. - - - - Max 6 11 11 - Unit ns ns ns SCLK 24-34 S3C2410X ELECTRICAL DATA Table 24-12. TFT LCD Controller Module Signal Timing Constants (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Vertical sync pulse width Vertical back porch delay Vertical front porch dealy VCLK pulse width VCLK pulse width high VCLK pulse width low Hsync setup to VCLK falling edge VDEN set up to VCLK falling edge VDEN hold from VCLK falling edge VD setup to VCLK falling edge VD hold from VCLK falling edge LEND width LEND hold from VCLK rising edge VSYNC setup to HSYNC falling edge VSYNC hold from HSYNC falling edge NOTES: 1. HSYNC period 2. VCLK period Symbol Tvspw Tvbpd Tvfpd Tvclk Tvclkh Tvclkl Tl2csetup Tde2csetup Tde2chold Tvd2csetup Tvd2chold Tlewidth Tle2chold Tf2hsetup Tf2hhold Min VSPW + 1 VBPD+1 VFPD+1 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 - 3 HSPW + 1 HBPD + HFPD + HOZVAL + 3 Typ - - - - - - - - - - - 1 - - - Max - - - - - - - - - - - - - - - Units Phclk (note1) Phclk Phclk Pvclk (note2) Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk Pvclk ns Pvclk Pvclk Table 24-13. IIS Controller Module Signal Timing Constants (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter IISLRCK delay time IISDO delay time IISDI Input Setup time IISDI Input Hold time CODEC clock frequency Symbol tLRCK tSDO tSDIS tSDIH f CODEC Min 0.7 0.8 6.2 0.1 1/16 Typ. - - - - - Max 1.4 1.7 16.3 0.1 1 Unit ns ns ns ns f IIS_BLOCK 24-35 ELECTRICAL DATA S3C2410X Table 24-14. IIC BUS Controller Module Signal Timing (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter SCL clock frequency SCL high level pulse width SCL low level pulse width Bus free time between STOP and START START hold time SDA hold time SDA setup time STOP setup time Symbol f SCL tSCLHIGH tSCLLOW tBUF tSTARTS tSDAH tSDAS tSTOPH Min - std. 4.0 fast 0.6 std. 4.7 fast 1.3 std. 4.7 fast 1.3 std. 4.0 fast 0.6 std. 0 fast 0 std. 250 fast 100 std. 4.0 fast 0.6 Typ. - - - - - - - - Max std. 100 fast 400 - - - - std. - fast 0.9 - - Unit kHz s s s s s ns s NOTES: Std. means Standard Mode and fast means Fast Mode. 1. The IIC data hold time(tSDAH) is minimum 0ns. (IIC data hold time is minimum 0ns for standard/fast bus mode in IIC specification v2.1.) Please check the data hold time of your IIC device if it's 0 nS or not. 2. The IIC controller supports only IIC bus device(standard/fast bus mode), not C bus device. Table 24-15. SD/MMC Interface Transmit/Receive Timing Constants (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter SD Command output Delay time SD Command input Setup time SD Command input Hold time SD Data output Delay time SD Data input Setup time SD Data input Hold time Symbol tSDCD tSDCS tSDCH tSDDD tSDDS tSDDH Min 0.5 5.8 0.1 0.3 6.3 0.1 Typ. - - - - - - Max 1.3 15.2 0.1 0.6 15.3 0.1 Unit ns ns ns ns ns ns 24-36 S3C2410X ELECTRICAL DATA Table 24-16. SPI Interface Transmit/Receive Timing Constants (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter SPI MOSI Master Output Delay time SPI MOSI Slave Input Setup time SPI MOSI Slave Input Hold time SPI MISO Slave output Delay time SPI MISO Master Input Setup time SPI MISO Master Input Hold time Symbol tSPIMOD tSPISIS tSPISIH tSPISOD tSPIMIS tSPIMIH Min 1.0 0.1 0.8 8.2 5.6 0.1 Typ. - - - - - - Max 4.2 0.1 1.8 21.4 14.7 0.1 Unit ns ns ns ns ns ns Table 24-17. USB Electrical Specifications (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Supply Current Suspend Device Leakage Current Hi-Z state Input Leakage Input Levels Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High Capacitance Transceiver Capacitance CIN Pin to GND 20 pF VOL VOH RL of 1.5Kohm to 3.6V RL of 15Kohm to GND 2.8 0.3 3.6 V VDI VCM VSE | (D+) - (D-) | Includes VDI range 0.2 V 0.8 0.8 2.5 2.0 ILO 0V < VIN < 3.3V -10 10 A ICCS 10 A Symbol Condition Min Max Unit 24-37 ELECTRICAL DATA S3C2410X Table 24-18. USB Full Speed Output Buffer Electrical Characteristics (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Driver Characteristics Transition Time Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Drive Output Resistance TR TF TRFM VCRS ZDRV Steady state drive CL = 50pF CL = 50pF (TR / TF ) 4.0 4.0 90 1.3 28 2.0 2.0 110 2.0 43 % V ohm ns Symbol Condition Min Max Unit Table 24-19. USB Low Speed Output Buffer Electrical Characteristics (VDD = 1.8 V 0.15 V, TA = 0 to 70 C, VEXT = 3.3V 0.3V) Parameter Driver Characteristics Transition Time Rising Time Falling Time Rise/Fall Time Matching Output Signal Crossover Voltage TR TF TRFM VCRS CL = 50pF CL = 350pF CL = 50pF CL = 350pF (TR / TF ) 80 1.3 75 300 120 2.0 % V 75 300 ns Symbol Condition Min Max Unit 24-38 S3C2410X ELECTRICAL DATA Table 24-20. NAND Flash Interface Timing Constants (VDDi, VDDalive, VDDiarm = 1.8 V 0.15 V, TA = 0 to 70 C, VDDIO = 3.3V 0.3V) Parameter NFCON Chip Enable delay NFCON CLE delay NFCON ALE delay NFCON Write Enable delay NFCON Read Enable delay NFCON Write Data Setup time NFCON Write Data Hold time NFCON Read Data Setup requirement time NFCON Read Data Hold requirement time Symbol tCED tCLED tALED tWED tRED tWDS tWDH tRDS tRDH Min - - - - - - 1.7 0.3 0.3 Max 6.2 7.1 7.5 7.2 7.1 6.5 - - - Unit ns ns ns ns ns ns ns ns ns 24-39 ELECTRICAL DATA S3C2410X NOTES 24-40 S3C2410X MECHANICAL DATA 25 B MECHANICAL DATA PACKAGE DIMENSIONS 0.15 C x 2 14.00 A SAMSUNG 14.00 272-FBGA-1414 0.15 C x 2 0.35 0.05 0.10 C 0.45 0.05 1.16 0.12 MAX C TOLERANCE 0.10 Figure 25-1. 272-FBGA-1414 Package Dimension 1 (Top View) 25-1 MECHANICAL DATA S3C2410X 14.00 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U A1 INDEX MARK 0.80 x 16 = 12.80 0.05 0.80 0.80 272 - 0.45 0.05 0.15 M C A B 0.08 M C 14.00 TOLERANCE 0.10 Figure 25-2. 272-FBGA-1414 Package Dimension 2 (Bottom View) The recommended land open size is 390 - 410 m (0.39 - 0.41mm) diameter. 25-2 ARM920T PROCESSOR INTRODUCTION Appendix 1 ARM920T INTRODUCTION The ARM920T is a member of the ARM9TDMI family of general-purpose microprocessors, which includes: -- ARM9TDMI (ARM9TDMI core) -- ARM940T (ARM9TDMI core plus cache and protection unit) -- ARM920T (ARM9TDMI core plus cache and MMU). The ARM9TDMI processor core is a Harvard architecture device implemented using a five-stage pipeline consisting of fetch, decode, execute, memory and write stages, and can be provided as a stand-alone core which can be embedded into more complex devices. The stand-alone core has a simple bus interface that allows users to design their own caches/memory systems around it. The ARM9TDMI family of microprocessors supports both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. The ARM920T is a Harvard cache architecture processor which is targeted at multiprogrammer applications where full memory management, high performance, and low power are all-important. The separate instruction and data caches in this design are 16KB each in size, with an 8-word line length. The ARM920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission checks for instruction and data addresses. The ARM920T supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM920T also includes support for coprocessors, exporting the instruction and data buses along with simple handshaking signals. The ARM920T interface to the rest of the system is via unified address and data buses. This interface is compatible with the Advanced Microcontroller Bus Architecture (AMBA) bus scheme, either as a fully compliant AMBA bus master, or as a slave for production test. The ARM920T also has a TrackingICE mode which allows an approach similar to a conventional ICE mode of operation. 1-1 INTRODUCTION ARM920T PROCESSOR PROCESSOR FUNCTIONAL BLOCK DIAGRAM Shows the functional block diagram of the ARM920T External Coprocessor Interface Instruction Cache Instruction MMU IPA[31:0] IMVA[31:0] R13 ID[31:0] IVA[31:0] Trace Interface Port ARM9TDMI Processor Core (Integral EmbeddedICE) DAV[31:0] R13 DMVA[31:0] DPA[31:0] DD[31:0] AMBA Bus Interface Write Buffer ASB CP15 JTAG Data Cache Data MMU Write Back PA TAG RAM WBPA[31:0] DINDEX[31:0] Figure 1-1. ARM920T Functional Block Diagram 1-2 ARM920T PROCESSOR PROGRAMMER'S MODEL Appendix 2 PROGRAMMER'S MODEL ABOUT THE PROGRAMMER'S MODEL ARM920T incorporates the ARM9TDMI integer core, which implements the ARMv4T architecture. It executes the ARM and Thumb instruction sets, and includes Embedded ICE JTAG software debug features. The programmer's model of the ARM920T consists of the programmer's model of the ARM9TDMI with the following additions and modifications: * The ARM920T incorporates two coprocessors: -- CP14, which allows software access to the debug communications channel. The registers defined in CP14 are accessible with MCR and MRC instructions. -- The system control coprocessor (CP15), which provides additional registers that are used to configure and control the caches, MMU, protection system, the clocking mode and other system options of the ARM920T, such as big or little-endian operation. The registers defined in CP15 are accessible with MCR and MRC instructions. These are described in CP15 register map summary on page 2-4. * The ARM920T also features an external coprocessor interface which allows the attachment of a closely coupled coprocessor on the same chip, for example, a floating point unit. Registers and operations provided by any coprocessors attached to the external coprocessor interface will be accessible with appropriate coprocessor instructions. Memory accesses for instruction fetches and data loads and stores may be cached or buffered. Cache and write buffer configuration and operation is described in detail in following chapters. The MMU page tables which reside in main memory describe the virtual to physical address mapping, access permissions, and cache and write buffer configuration. These are created by the operating system software and accessed automatically by the ARM920T MMU hardware whenever an access causes a TLB miss. The ARM920T has a Trace Interface Port which allows the use of Trace hardware and tools for real-time tracing of instructions and data. * * * 2-1 PROGRAMMER'S MODEL ARM920T PROCESSOR ABOUT THE ARM9TDMI PROGRAMMER'S MODEL The ARM9TDMI processor core implements ARM v4T architecture, and so executes the ARM 32-bit instruction set and the compressed Thumb 16-bit instruction set. The programmer's model is fully described in the ARM Architecture Reference Manual. The ARM9TDMI Technical Reference Manual gives implementation details including instruction execution cycle times. The ARM v4T architecture specifies a small number of implementation options. The options selected in the ARM9TDMI implementation are listed in Table 2-1. For comparison, the options selected for the ARM7TDMI implementation are also shown Table 2-1. ARM9TDMI Implementation Option Processor core ARM7TDMI ARM9TDMI v4T v4T ARM architecture Data abort model Base updated Base restored Value stored by direct STR, STRT, STM of PC Address of Inst + 12 Address of Inst + 12 The ARM9TDMI is code-compatible with the ARM7TDMI, with two exceptions: * * The ARM9TDMI implements the base restored data abort model, which significantly simplifies the software data abort handler. The ARM9TDMI fully implements the instruction set extension spaces added to the ARM (32-bit) instruction set in architecture v4 and v4T. These differences are explained in more detail below. DATA ABORT MODEL The base restored data abort model differs from the base updated data abort model implemented by ARM7TDMI. The difference in the data abort model affects only a very small section of operating system code, the data abort handler. It does not affect user code. With the base restored data abort model, when a data abort exception occurs during the execution of a memory access instruction, the base register is always restored by the processor hardware to the value the register contained before the instruction was executed. This removes the need for the data abort handler to unwind any base register update which may have been specified by the aborted instruction. 2-2 ARM920T PROCESSOR PROGRAMMER'S MODEL INSTRUCTION SET EXTENSION SPACES All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception. That is, ARM instructions with opcode[27:25] = 0b011 and opcode[4] = 1 are undefined on all ARM processors including the ARM9TDMI and ARM7TDMI. ARM architecture v4 and v4T also introduced a number of instruction set extension spaces to the ARM instruction set. These are: * * * * arithmetic instruction extension space control instruction extension space coprocessor instruction extension space load/store instruction extension space. Instructions in these spaces are undefined (they cause an undefined instruction exception). The ARM9TDMI fully implements all the instruction set extension spaces defined in ARM architecture v4T as undefined instructions, allowing emulation of future instruction set additions. The system control coprocessor (CP15) allows configuration and control of the caches, MMU, protection system and clocking mode of the ARM920T. The ARM920T coprocessor 15 registers are described under the following sections: * * * * * * * * * * * * * * * * * Accessing CP15 registers on page 2-5 Register 0: ID code register on page 2-7 Register 0: Cache type register on page 2-8 Register 1: Control register on page 2-10 Register 2: Translation table base (TTB) register on page 2-12 Register 3: Domain access control register on page 2-13 Register 4: Reserved on page 2-14 Register 5: Fault status registers on page 2-14 Register 6: Fault address register on page 2-15 Register 7: Cache operations on page 2-15 Register 8: TLB operations on page 2-18 Register 9: Cache lock down register on page 2-19 Register 10: TLB lock down register on page 2-21 Registers 11 -12 & 14: Reserved on page 2-22 Register 13: Process ID on page 2-22 Addresses in ARM920T on page 2-6 Register 15: Test configuration register on page 2-24. 2-3 PROGRAMMER'S MODEL ARM920T PROCESSOR CP15 REGISTER MAP SUMMARY CP15 defines 16 registers. The register map for CP15 is shown in Table 2-2 Table 2-2. CP15 Register Map Register 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ID code (1) Cache type (1) Control Translation table base Domain access control Unpredictable Fault status (2) Fault address Unpredictable Unpredictable Cache lockdown (2) TLB lock down (2) Unpredictable Unpredictable Process ID Unpredictable Test configuration Read Unpredictable Unpredictable Control Translation table base Domain access control Unpredictable Fault status (2) Fault address Cache operations TLB operations Cache lockdown (2) TLB lock down (2) Unpredictable Unpredictable Process ID Unpredictable Test configuration Write NOTES: 1. Register location 0 provides access to more than one register. The register accessed depends upon the value of the opcode_2 field. See the register description for details. 2. Separate registers for instruction and data. See the register description for details. 2-4 ARM920T PROCESSOR PROGRAMMER'S MODEL ACCESSING CP15 REGISTERS Throughout this section the following terms and abbreviations are used. Table 2-3. CP15 Abbreviations Term Unpredictable Abbreviation UNP Description For reads, the data returned when reading from this location is unpredictable; it could have any value. For writes, writing to this location will cause unpredictable behavior, or an unpredictable change in device configuration. Should be zero SBZ When writing to this location, all bits of this field should be 0. In all cases, reading from, or writing any data values to any CP15 registers, including those fields specified as unpredictable or should be zero, will not cause any permanent damage. All CP15 register bits that are defined and contain state, are set to zero by BnRES except V-Bit in register 1, which takes the value of macrocell input VINITHI when BnRES is asserted. CP15 registers can only be accessed with MRC and MCR instructions in a privileged mode. The instruction bit pattern of the MCR and MRC instructions is shown in Figure 2-1. The assembler for these instructions is MCR/MRC{cond} P15,opcode_1,Rd,CRn,CRm,opcode_2 31 Cond 28 27 26 25 24 23 21 20 19 CRn 16 15 Rd 12 11 10 9 8 7 543 CRm 0 1 1 1 0 opcode1 L 1 1 1 1 opcode2 1 Figure 2-1. CP15 MRC and MCR Bit Pattern Instructions CDP, LDC and STC, along with unprivileged MRC and MCR instructions to CP15 will cause the undefined instruction trap to be taken. The CRn field of MRC and MCR instructions specifies the coprocessor register to access. The CRm field and opcode_2 field are used to specify a particular action when addressing registers. Attempting to read from a non-readable register, or writing to a non-writable register will cause unpredictable results. The opcode_1, opcode_2 and CRm fields should be zero, except when the values specified are used to select the desired operations, in all instructions which access CP15. Using other values will result in unpredictable behavior. 2-5 PROGRAMMER'S MODEL ARM920T PROCESSOR Addresses in ARM920T Three distinct types of address exist in an ARM920T system: * * * virtual address (VA) modified virtual address (MVA) physical address (PA). Below is an example of the address manipulation when the ARM9TDMI requests an instruction. 1) The VA of the instruction (IVA) is issued by the ARM9TDMI. 2) This is translated by the ProcID to the instruction MVA (IMVA). It is the IMVA that the instruction cache and MMU see. 3) If the protection check carried out by the IMMU on the IMVA does not abort and the IMVA tag is in the instruction cache the instruction data is returned to the ARM9TDMI. 4) If the instruction cache misses (the IMVA tag is not in the instruction cache) then the IMMU performs a translation to produce the instruction PA (IPA). This address is given to the AMBA bus interface to perform an external access Table 2-4. Address Types in ARM920 Domain Address Virtual Domain Caches & TLBs Modified Virtual AMBA bus Physical 2-6 ARM920T PROCESSOR PROGRAMMER'S MODEL REGISTER 0: ID CODE REGISTER This is a read-only register which returns a 32-bit device ID code. The ID code register is accessed by reading CP15 register 0 with the opcode_2 field set to any value other than 1 (the CRm field should be zero when reading). For example: MRC p15,0,Rd,c0,c0,0; returns ID register The contents of the ID code are shown in Table 2-5. Table 2-5. Register 0: ID Code Register bits 31:24 23:20 19:16 15:4 3:0 Implementor Specification revision Architecture version (4T) Part number Layout revision Function 0x41 0x1 0x2 0x920 0x0 Value 2-7 PROGRAMMER'S MODEL ARM920T PROCESSOR REGISTER 0: CACHE TYPE REGISTER This is a read-only register which contains information about the size and architecture of the caches, allowing operating systems to establish how to perform such operations as cache cleaning and lockdown. Future ARM cached processors will contain this register, allowing RTOS vendors to produce future-proof versions of their operating systems. The cache type register is accessed by reading CP15 register 0 with the opcode_2 field set to 1. For example: MRC p15,0,Rd,c0,c0,1; returns cache details The format of the register is shown in Table 2-6. Table 2-6. Cache Type Register Format Register Bits 31:29 28:25 24 23:21 20:18 17:15 14 13:12 11:9 8:6 5:3 2 1:0 Reserved Cache type Harvard/Unified Reserved DCache size DCache associativity Reserved DCache words per line Reserved ICache size ICache Associativity Reserved ICache words per line Function 000 0110 1 (defines Harvard cache) 000 101 (defines 16KB) 110 (defines 64 way) 0 10 (defines 8 words per line) 000 101 (defines 16KB) 110 (defines 64 way) 0 10 (defines 8 words per line) Value Bits [28:25] indicate which major cache class the implementation falls into. 0x6 means that the cache provides: * * * Cache-clean-step operation Cache-flush-step operation Lock down facilities 2-8 ARM920T PROCESSOR PROGRAMMER'S MODEL Bits [20:18] give the data cache size. Bits [8:6] give the instruction cache size. Table 2-7 on page 2-9 shows the meaning of values used for cache size encoding. Table 2-7. Cache Size Encoding Bits [20:18]/Bits [8:6] 000 001 010 011 100 101 110 111 Cache Size 512B 1KB 2KB 4KB 8KB 16KB 32KB 64KB Bits [17:15] give the data cache associativity. Bits [5:3] give the instruction cache associativity. Table 2-8 on page 2-9 shows the meaning of values used for cache associativity encoding. Table 2-8. Cache size encoding Bits [20:18]/Bits [8:6] 000 001 010 011 100 101 110 111 Cache Size 512B 1KB 2KB 4KB 8KB 16KB 32KB 64KB Bits [13:12] give the data cache line length. Bits [1:0] give the instruction cache line length. 2-9 PROGRAMMER'S MODEL ARM920T PROCESSOR Table 2-9 shows the meaning of values used for line length encoding Table 2-9. Line Length Encoding Bits [13:12]/Bits [1:0] 00 01 10 11 Words Per Line 2 4 8 16 REGISTER 1: CONTROL REGISTER This register contains the control bits of the ARM920T. All reserved bits should either be written with zero or one, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read. To read and write this register: MRC p15, 0, Rd, c1, c0, 0; read control register MCR p15, 0, Rd, c1, c0, 0; write control register All defined control bits are set to zero on reset except the V-Bit which is set to zero at reset if the VINITHI pin is LOW, or one if the VINITHI pin is HIGH. The functions of the control bits are shown in Table 2-10. 2-10 ARM920T PROCESSOR PROGRAMMER'S MODEL Table 2-10. Control Register 1-bit Functions Register Bits 31 30 29:15 14 13 12 11:10 9 8 7 6:3 2 1 C bit A bit R bit S bit B bit - RR bit V bit I bit - Name iA bit nF bit - Function Asynchronous clock select notFastBus select Reserved Round robin replacement Base location of exception registers Instruction cache enable Reserved ROM protection System protection Big-endian/little-endian Reserved Data cache enable Alignment fault enable Value See Table 2-11 on page 2-11. See Table 2-11 on page 2-11. Read = Unpredictable Write = Should be zero 0 = Random replacement 1 = Round robin replacement 0 = Low addresses = 0x0000 0000 1 = High addresses = 0xFFFF 0000 0 = Instruction cache disabled 1 = Instruction cache enabled Read = 00 Write = 00 This bit modifies the MMU protection system. See Table 3-6 on page 3-20 This bit modifies the MMU protection system. See Table 3-6 on page 3-20 0 = Little-endian operation 1 = Big-endian operation Read = 1111 Write = 1111 0 = Data cache disabled 1 = Data cache enabled Data address alignment fault checing. 0 = Fault checking disabled 1 = Fault checking enabled 0 = MMU disabled 1 = MMU enabled 0 M bit MMU enable Register 1 bits 31:30 select the clocking mode of the ARM920T, as shown in Table 2-11. Table 2-11. Clocking Modes Clocking Mode FastBus mode Reserved Synchronous Asynchronous iA 0 1 0 1 nF 0 0 1 1 2-11 PROGRAMMER'S MODEL ARM920T PROCESSOR Enabling the MMU Care must be taken with the address mapping of the code sequence used to enable the MMU, see Enabling the MMU on page 3-25. See Instruction cache enable/disable on page 4-3 and Data cache and write buffer enable/disable on page 4-6 for restrictions and effects of having caches enabled with the MMU disabled REGISTER 2: TRANSLATION TABLE BASE (TTB) REGISTER This is the translation table base register, for the currently active first level translation table. The contents of register 2 are shown in Table 2-12. Table 2-12. Register 2: Translation Table Base Register Bits 31:14 13:0 Function Pointer to first level translation table base. Read/write Reserved Read = Unpredictable Write = Should be zero Reading from register 2 returns the pointer to the currently active first level translation table in bits[31:14]. Writing to register 2 updates the pointer to the first level translation table from the value in bits[31:14] of the written value. Bits[13:0] should be zero when written, and are unpredictable when read. The following instructions can be used to access the TTB: MRC p15, 0, Rd, c2, c0, 0; read TTB register MCR p15, 0, Rd, c2, c0, 0; write TTB register 2-12 ARM920T PROCESSOR PROGRAMMER'S MODEL REGISTER 3: DOMAIN ACCESS CONTROL REGISTER Register 3 is the read/write domain access control register consisting of sixteen 2-bit fields. Each of these 2-bit fields defines the access permissions for the domains shown in Table 2-13. Table 2-13. Register 3: Domain Access Control Register Bits 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Domain D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 The encoding of the two bit domain access permission field is given in Table 3-5 on page 3-19. The following instructions can be used to access the domain access control register: MRC p15, 0, Rd, c3, c0, 0; read domain 15:0 access permissions MCR p15, 0, Rd, c3, c0, 0; write domain 15:0 access permissions 2-13 PROGRAMMER'S MODEL ARM920T PROCESSOR REGISTER 4: RESERVED Accessing (reading or writing) this register will cause unpredictable behavior. REGISTER 5: FAULT STATUS REGISTERS Register 5 is the fault status register (FSR). The FSR contains the source of the last data fault, indicating the domain and type of access being attempted when the data abort occurred. Table 2-14. Fault Status Register Register Bits 31:9 8 7:4 3:0 0 when read/SBZ for write. Domain being accessed when fault occurred (D15-D0). Fault type. Description UNP when read/SBZ for write. The fault type encoding is shown in Fault address and fault status registers on page 3-18. The data FSR is defined in ARM architecture v4T. Additionally, a pipelined prefetch FSR is available, for debug purposes only. The pipeline matches that of the ARM9TDMI. The following instructions can be used to access the data and prefetch FSR: MRC p15, 0, Rd, c5, c0, 0 ;read data FSR value MCR p15, 0, Rd, c5, c0, 0 ;write data FSR value MRC p15, 0, Rd, c5, c0, 1 ;read prefetch FSR value MCR p15, 0, Rd, c5, c0, 1 ;write prefetch FSR value The ability to write to the FSR is useful for a debugger to restore the value of the FSR. The register should be written using the read-modify-write method. Bits[31:8] should be zero. 2-14 ARM920T PROCESSOR PROGRAMMER'S MODEL REGISTER 6: FAULT ADDRESS REGISTER Register 6 is the fault address register (FAR) which contains the modified virtual address of the access being attempted when the last fault occurred. The FAR is only updated for data faults, not for prefetch faults. (The address for a prefetch fault can be found in R14.) The following instructions can be used to access the FAR: MRC p15, 0, Rd, c6, c0, 0 ;read FAR data MCR p15, 0, Rd, c6, c0, 0 ;write FAR data The ability to write to the FAR is intended for a debugger to restore a previous state. REGISTER 7: CACHE OPERATIONS Register 7 is a write-only register used to manage the instruction and data caches, ICache and DCache. The cache operations provided by register 7 are described in Table 2-15. Table 2-15. Function Descriptions Register 7 Function Invalidate cache Invalidate single entry using modified virtual address Clean D single entry using either index or modified virtual address Clean and Invalidate D entry using either index or modified virtual address Prefetch cache line Description Invalidates all cache data, including any dirty data (note). Use with caution. Invalidates a single cache line, discarding any dirty data (note). Use with caution. Writes the specified cache line to main memory if the line is marked valid and dirty and marks the line as not dirty (note). The valid bit is unchanged. Writes the specified cache line to main memory if the line is marked valid and dirty (note). The line is marked not valid. Performs an ICache lookup of the specified modified virtual address. If the cache misses, and the region is cacheable, a linefill will be performed. NOTE: Dirty data is data that has been modified in the cache but not yet written to main memory. 2-15 PROGRAMMER'S MODEL ARM920T PROCESSOR The function of each cache operation is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 7. Writing other opcode_2 or CRm values is unpredictable. Reading from CP15 register 7 is unpredictable. Table 2-16 on page 2-16 shows instructions that can be used to perform cache operations with register 7 Table 2-16. Cache Operations Register 7 Function Invalidate ICache & DCache Invalidate ICache Invalidate ICache single entry (using MVA) Prefetch ICache line (using MVA) Invalidate DCache Invalidate DCache single entry (using MVA) Clean DCache single entry (using MVA) Clean and Invalidate DCache entry (using MVA) Clean DCache single entry (using index) Clean and Invalidate DCache entry (using index) Drain write buffer (1) Data SBZ SBZ MVA format MVA format SBZ MVA format MVA format MVA format Index format Index format SBZ SBZ Instruction MCR p15,0,Rd,c7,c7,0 MCR p15,0,Rd,c7,c5,0 MCR p15,0,Rd,c7,c5,1 MCR p15,0,Rd,c7,c13,1 MCR p15,0,Rd,c7,c6,0 MCR p15,0,Rd,c7,c6,1 MCR p15,0,Rd,c7,c10,1 MCR p15,0,Rd,c7,c14,1 MCR p15,0,Rd,c7,c10,2 MCR p15,0,Rd,c7,c14,2 MCR p15,0,Rd,c7,c10,4 MCR p15,0,Rd,c7,c0,4 Wait for interrupt (2) NOTES: 1. Will stop execution until the write buffer has drained. 2. Will stop execution in a LOW power state until an interrupt occurs. 2-16 ARM920T PROCESSOR PROGRAMMER'S MODEL The operations which can be carried out upon a single cache line identify the line using the data passed in the MCR instruction. The data is interpreted using one of the following formats: 31 Modified virtual address 543210 00000 SBZ Figure 2-2. Register 7 MVA Format 31 Index 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 543210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Segment 0 0 0 0 0 SBZ SBZ Figure 2-3. Register 7 Index Format The use of register 7 is discussed in Chapter 4 Caches, Write Buffer and Physical Address TAG (PATAG) RAM. 2-17 PROGRAMMER'S MODEL ARM920T PROCESSOR REGISTER 8: TLB OPERATIONS Register 8 is a write-only register used to manage the translation lookaside buffers (TLBs), the instruction TLB and the data TLB. Five TLB operations are defined and the function to be performed is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 8. Writing other opcode_2 or CRm values is unpredictable. Reading from CP15 register 8 is unpredictable. Table 2-17 on page 2-18 shows instructions that can be used to perform TLB operations using register 8. Table 2-17. TLB Operations Register 8 Function Invalidate TLB(s) Invalidate I TLB Invalidate I TLB single entry (using MVA) Invalidate D TLB Invalidate D TLB single entry (using MVA) SBZ SBZ MVA format SBZ MVA format Data Instruction MCR p15,0,Rd,c8,c7,0 MCR p15,0,Rd,c8,c5,0 MCR p15,0,Rd,c8,c5,1 MCR p15,0,Rd,c8,c6,0 MCR p15,0,Rd,c8,c6,1 NOTE: These functions invalidate all the un-preserved entries in the TLB. Invalidate TLB single entry functions invalidate any TLB entry corresponding to the modified virtual address given in Rd, regardless of its preserved state. See Register 10: TLB lock down register on page 2-21 Figure 2-4 shows the modified virtual address format used for operations on single entry TLB lines using register 8. 31 Modified virtual address 10 9 8 7 6 5 4 3 2 1 0 0000000000 SBZ Figure 2-4. Register 8 MVA Format 2-18 ARM920T PROCESSOR PROGRAMMER'S MODEL REGISTER 9: CACHE LOCK DOWN REGISTER Register 9 is the cache lock down register. The cache lock down register is 0x0 on reset. The cache lock down register allows software to control which cache line in the ICache or DCache respectively is loaded for a linefill and to prevent lines in the ICache or DCache from being evicted during a linefill, locking them into the cache. There is a register for each of the ICache and DCache, the value of opcode_2 determines which cache register to access: opcode_2 = 0x0 causes the DCache register to be accessed opcode_2 = 0x1 causes the ICache register to be accessed. The Opcode_1 and CRm fields should be zero. Reading CP15 register 9 returns the value of the cache lock down register, which is the base pointer for all cache segments. NOTE: Only bits [31:26] are returned. Bits [25:0] are unpredictable. Writing CP15 register 9 updates the cache lock down register, both the base and the current victim pointer for all cache segments. Bits [25:0] should be zero. The victim counter specifies the cache line to be used as the victim for the next linefill. This is incremented using either a random or round-robin replacement policy, determined by the state of the RR-bit in register 1. The victim counter generates values in the range (base to 63). This locks lines with index values in the range (0 to base-1). If base = 0, there are no locked lines. Writing to CP15 register 9 updates the base pointer and the current victim pointer. The next linefill will use and then increment the victim pointer. The victim pointer will continue incrementing on linefills and will wrap around to the base pointer. For example, setting the base pointer to 0x3 prevents the victim pointer from selecting entries 0x0 to 0x2, locking them into the cache. Load a cache line into ICache line 0 and lock it down: MCR to CP15 register 9, opcode_2 = 0x1, Victim=Base=0x0 MCR I prefetch. Assuming the ICache misses, a linefill will occur to line 0. MCR to CP15 register 9, opcode_2 = 0x1, Victim=Base=0x1 Further ICache linefills will now occur into lines 1 - 63. Load a cache line into DCache line 0 and lock it down: MCR to CP15 register 9, opcode_2 = 0x0, Victim=Base=0x0 Data load (LDR/LDM). Assuming the DCache misses, a linefill will occur to line 0. MCR to CP15 register 9, opcode_2 = 0x0, Victim=Base=0x1 Further DCache linefills will now occur into lines 1 - 63. NOTE: Writing CP15 register 9, with the CRm field set to 0b0001, updates the current victim pointer only for the specified segment only. Bits [31:26] specify the victim; bits [7:5] specify the segment (for a 16KB cache) and all other bits should be zero. This encoding is intended for debug use. It is not necessary and not advised, to use this encoding. 2-19 PROGRAMMER'S MODEL ARM920T PROCESSOR Figure 2-5 shows the format of bits in register 9 31 Index 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000000000000000000000 UNP/SBZ Figure 2-5. Register 9 Table 2-18 shows the instructions needed to access the cache lock down register: Table 2-18. Accessing the Cache Lock Down Register 9 Function Read DCache lock down base Write DCache victim and lockdown base Read ICache lock down base Write ICache victim and lockdown base Base Victim=Base Base Victim=Base Data Instruction MRC p15,0,Rd,c9,c0,0 MCR p15,0,Rd,c9,c0,0 MRC p15,0,Rd,c9,c0,1 MCR p15,0,Rd,c9,c0,1 2-20 ARM920T PROCESSOR PROGRAMMER'S MODEL REGISTER 10: TLB LOCK DOWN REGISTER Register 10 is the TLB lock down register. The TLB lock down register is 0x0 on reset. There is a TLB lock down register for each of the TLBs, the value of opcode_2 determines which TLB register to access: opcode_2 = 0x0 causes the D TLB register to be accessed opcode_2 = 0x1 causes the I TLB register to be accessed. Reading CP15 register 10 returns the value of the TLB lock down counter base register, the current victim number and the preserve bit (P bit). Note that bits [19:1] are unpredictable when read. Writing CP15 register 10 updates the TLB lock down counter base register, the current victim pointer and the state of the preserve bit. Bits [19:1] should be zero when written. Table 2-19 shows the instructions needed to access the TLB lock down register. Table 2-19. Accessing the TLB Lock Down Register 10 Function Read D TLB lock down Write D TLB lock down Read I TLB lock down Write I TLB lock down Figure 2-6 shows the format of bits in register 10. Data TLB lock-down TLB lock-down TLB lock-down TLB lock-down Instruction MRC p15,0,Rd,c10,c0,0 MCR p15,0,Rd,c10,c0,0 MRC p15,0,Rd,c10,c0,1 MCR p15,0,Rd,c10,c0,1 31 Base 26 25 Victim 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000000P UNP/SBZ Figure 2-6. Register 10 The entries in the TLBs are replaced using a round robin replacement policy. This is implemented using a victim counter which counts from entry 0 up to 63 and then wraps back round to the base value and continues counting, wrapping around to the base value from 63 each time. There are two mechanisms available for ensuring entries are not removed from the TLB: Locking an entry down prevents it from being selected for overwriting during a table walk, this is achieved by programming the base value to which the victim counter reloads. For example, if the bottom 3 entries (0-2) are to be locked down, the base counter should be programmed to 3. An entry can also be preserved during an Invalidate All instruction. This is done by ensuring the P bit is set when the entry is loaded into the TLB. 2-21 PROGRAMMER'S MODEL ARM920T PROCESSOR Load a single entry into I TLB location 0, make it immune to Invalidate All and lock it down: MCR to CP15 register 10, opcode_2 = 0x1, Base Value = 0, Current Victim = 0, P = 1 MCR I prefetch. Assuming an I TLB miss occurs, then entry 0 will be loaded. MCR to CP15 register 10, opcode_2 = 0x1, Base Value = 1, Current Victim = 1, P = 0 Load a single entry into D TLB location 0, make it immune to Invalidate All and lock it down: MCR to CP15 register 10, opcode_2 = 0x0, Base Value = 0, Current Victim = 0, P = 1 Data load (LDR/LDM) or store (STR/STM). Assuming a D TLB miss occurs, then entry 0 will be loaded. MCR to CP15 register 10, opcode_2 = 0x0, Base Value = 1, Current Victim = 1, P = 0 REGISTERS 11-12 & 14: RESERVED Accessing (reading or writing) any of these registers will cause unpredictable behavior. REGISTER 13: PROCESS ID Register 13 is the process identifier register. The process identifier register is 0x0 on reset. Reading from CP15 register 13 returns the value of the process identifier. Writing CP15 register 13 updates the process identifier to the value in bits [31:25]. Bits [24:0] should be zero. Register 13 bit assignments are shown in Figure 2-7. 31 Proc ID 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000000000000 SBZ Figure 2-7. Register 13 Register 13 can be accessed using the following instructions: MRC p15, 0, Rd, c13, c0, 0 ;read process identifier MCR p15, 0, Rd, c13, c0, 0 ;write process identifier 2-22 ARM920T PROCESSOR PROGRAMMER'S MODEL Using the process Identifier (ProcID) Addresses issued by the ARM9TDMI core in the range 0 to 32MB are translated by CP15 register 13, the ProcID register. Address A becomes A + (ProcID x 32MB). It is this translated address that is seen by both the Caches and MMU. Addresses above 32MB undergo no translation. This is shown in Figure 2-8 on page 2-23 . The ProcID is a seven bit field, enabling 64 x 32MB processes to be mapped. NOTES If ProcID is zero, as it is on reset, then there is a flat mapping between the ARM9TDMI and the Caches and MMU. Virtual address (VA) issued by ARM9TDMI 4GB Modified virtual address (MVA) input to caches and MMU 63 4GB 2 1 32MB 0 C13 0 64MB 32MB 0 Figure 2-8. Address Mapping Using CP15 Register 13 2-23 PROGRAMMER'S MODEL ARM920T PROCESSOR Changing the ProcID - performing a fast context switch A fast context switch is done by writing to CP15 register 13. The contents of the caches and TLBs do not have to be flushed after a fast context switch because they still hold valid address tags. It should be noted that the two instructions after the MCR to write the ProcID will have been fetched with the old ProcID: {ProcID = 0} MOV r0, #1:SHL:25 MCR p15,0,r0,c13,c0,0 A1 A2 A3 ; Fetched with ProcID = 0 ; Fetched with ProcID = 0 ; Fetched with ProcID = 0 ; Fetched with ProcID = 0 ; Fetched with ProcID = 1 REGISTER 15: TEST CONFIGURATION REGISTER Register 15 is used for test purposes. Accessing (reading or writing) this register will cause the ARM920T to have unpredictable behavior. 2-24 ARM920T PROCESSOR MMU Appendix 3 MMU ABOUT THE MMU ARM920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI. The MMU is controlled from a single set of two-level page tables stored in main memory, and are enabled by M-Bit in CP15 register 1, providing a single address translation and protection scheme. The instruction and data TLBs in the MMU can be independently locked and flushed. The MMU features are: * * * * * * * * * * * standard ARM V4 MMU mapping sizes, domains, and access protection scheme mapping sizes are 1MB sections, 64KB large pages, 4KB small pages and new 1KB tiny pages access permissions for sections access permissions for large pages and small pages can be specified separately for each quarter of the page (these quarters are called sub-pages) 16 domains implemented in hardware 64 entry instruction TLB and 64 entry data TLB hardware page table walks round-robin replacement algorithm (also called cyclic) invalidate whole TLB via CP15 Register 8 invalidate TLB entry, selected by modified virtual address, via CP15 register 8 independent lockdown of instruction TLB and data TLB via CP15 register 10. ACCESS PERMISSIONS AND DOMAINS For large and small pages, access permissions are defined for each sub-page (1KB for small pages, 16KB for large pages). Sections and tiny pages have a single set of access permissions. All regions of memory have an associated domain. A domain is the primary access control mechanism for a region of memory and defines the conditions in which an access can proceed. The domain determines whether: the access permissions are used to qualify the access the access is unconditionally allowed to proceed the access is unconditionally aborted. In the latter two cases, the access permission attributes are ignored. There are 16 domains, which are configured using the domain access control register. 3-1 MMU ARM920T PROCESSOR TRANSLATED ENTRIES Each TLB caches 64 translated entries. During CPU memory accesses, the TLB provides the protection information to the access control logic. If the TLB contains a translated entry for the modified virtual address, the access control logic determines whether access is permitted: * * * If access is permitted and an off-chip access is required, the MMU outputs the appropriate physical address corresponding to the modified virtual address. If access is permitted and an off-chip access is not required, the cache services the access. If access is not permitted, the MMU signals the CPU core to abort. If a TLB misses (it does not contain an entry for the virtual address) the translation table walk hardware is invoked to retrieve the translation information from a translation table in physical memory. Once retrieved, the translation information is written into the TLB, possibly overwriting an existing value. The entry to be written is chosen by cycling sequentially through the TLB locations. To enable use of TLB locking features, the location to be written can be specified using CP15 register 10, TLB lockdown. When the MMU is turned off (as happens on reset), no address mapping occurs and all regions are marked as non-cacheable and non-bufferable. See About the caches and write buffer on page 4-1. 3-2 ARM920T PROCESSOR MMU MMU PROGRAM ACCESSIBLE REGISTERS Table 3-1 shows system control coprocessor (CP15) registers which are used, in conjunction with page table descriptors stored in memory, to determine the operation of the MMU Table 3-1. CP15 Register Functions Register Control register 1 Number Bits M, A, S, R Register description Contains bits to enable the MMU (M bit), enable data address alignment checks (A bit) and to control the access protection scheme (S bit and R bit). Holds the physical address of the base of the translation table maintained in main memory. This base address must be on a 16KB boundary and is common to both TLBs. Comprises sixteen 2-bit fields. Each field defines the access control attributes for one of 16 domains (D15-D0). Indicates the cause of a data and prefetch abort and the domain number of the aborted access, when an abort occurs. Bits 7:4 specify which of the 16 domains (D15-D0) was being accessed when a fault occurred. Bits 3:0 indicate the type of access being attempted. The value of all other bits is unpredictable. The encoding of these bits is shown in Table 3-4 on page 3-18 . Holds the virtual address associated with the access that caused the data abort. See Table 3-4 on page 3-18 for details of the address stored for each type of fault. ARM9TDMI Register 14 can be used to determine the virtual address associated with a prefetch abort. TLB operations register 8 31:0 Writing to this register causes the MMU to perform TLB maintenance operations; either invalidating all the (unpreserved) entries in the TLB, or invalidating a specific entry. Allows specific page table entries to be locked into the TLB and the TLB victim index to be read/written: opcode 2 = 0x0 accesses the D TLB lock down register opcode 2 = 0x1 accesses the I TLB lock down register. Locking entries in the TLB guarantees that accesses to the locked page or section can proceed without incurring the time penalty of a TLB miss. This allows the execution latency for time-critical pieces of code such as interrupt handlers to be minimized. Translation table base register 2 31:14 Domain access control register 3 31:0 Fault status register 5 (I & D) 7:0 Fault address register 6 (D) 31:0 TLB lock down register 10 (I & D) 31:20 & 0 3-3 MMU ARM920T PROCESSOR All the CP15 MMU registers, except register 8, contain state and can be read using MRC instructions and written using MCR instructions. Registers 5 and 6 are also written by the MMU during a data abort. Writing to Register 8 causes the MMU to perform a TLB operation, to manipulate TLB entries. This register cannot be read. The instruction TLB (I TLB) and data TLB (D TLB) both have a copy of register 10, the opcode_2 field in the CP15 instruction is used to determine which one is accessed. The system control coprocessor (CP15) is described in Programmer's Model on page 2-1. Details of register format and the coprocessor instructions to access them are given there. ADDRESS TRANSLATION The MMU translates virtual addresses generated by the CPU core (and by CP15 register 13) into physical addresses to access external memory. It also derives and checks the access permission, using a translation lookaside buffer (TLB). The MMU table walking hardware is used to add entries to the TLB. The translation information, which comprises both the address translation data and the access permission data, resides in a translation table located in physical memory. The MMU provides the logic needed to traverse this translation table and load entries into the TLB. There are up to two stages to the hardware table walking (and hence permission checking) process. The number of stages depends on whether the address in question has been marked as a section-mapped access or a pagemapped access. There is one size of section and three sizes of page-mapped access (large pages, small pages and tiny pages). The translation process always starts out in the same way, with a level one fetch. A sectionmapped access requires only a level one fetch, but a page-mapped access requires a subsequent level two fetch. 3-4 ARM920T PROCESSOR MMU Level one fetch Translation table Level two fetch TTB base Section base Section Indexed by modified virtual address bits [31:20] Indexed by modified virtual address bits [19:0] Large page base Large page 4096 entries Coarse page table base 1MB Coarse page table Indexed by modified virtual address bits [15:0] 64KB Small page base Indexed by modified virtual address bits [19:12] Small page 256 entries Tiny page table base Fine page table Indexed by modified virtual address bits [11:0] 4KB Tiny page base Indexed by modified virtual address bits [19:10] Tiny page 1024 entries Indexed by modified virtual address bits [9:0] 1KB Figure 3-1. Translating Page Tables 3-5 MMU ARM920T PROCESSOR HARDWARE TRANSLATION PROCESS TRANSLATION TABLE BASE The hardware translation process is initiated when the TLB does not contain a translation for the requested modified virtual address. The translation table base (TTB) register points to the base address of a table in physical memory which contains section and/or Page descriptors. The 14 low-order bits of the TTB register are set to zero on a read and the table must reside on a 16KB boundary. 31 Translation table base 14 13 0 Figure 3-2. Translation Table Base Register The translation table has up to 4096 x 32-bit entries, each describing 1MB of virtual memory. This allows up to 4GB of virtual memory to be addressed. Figure 3-1 on page 3-5 illustrates the table walk process. 3-6 ARM920T PROCESSOR MMU LEVEL ONE FETCH Bits 31:14 of the translation table base register are concatenated with bits 31:20 of the modified virtual address to produce a 30-bit address as illustrated in Figure 3-3 on page 3-7. This address selects a 4-byte translation table entry which is a level one descriptor for either a section or a page table. Modified virtual address 31 Table index 20 19 Section index 0 Translation table base 31 Translation base 12 18 31 Translation base 14 13 Table index 210 00 14 13 0 31 Level one descriptor 0 Figure 3-3. Accessing the Translation Table Level One Descriptors 3-7 MMU ARM920T PROCESSOR LEVEL ONE DESCRIPTOR The level one descriptor returned is either a section descriptor a coarse page table descriptor, or a fine page table descriptor. A section descriptor provides the base address of a 1MB block of memory. The page table descriptors provide the base address of a page table that contains level two descriptors. There are two sizes of page table: * * coarse page tables have 256 entries, splitting the 1MB the table describes into 4KB blocks fine page tables have 1024 entries, splitting the 1MB the table describes into 1KB blocks 31 20 19 12 11 10 9 8 543210 00 Fault Coarse page table Section Fine page table Coarse page table base address Section base address Fine page table base address AP Domain Domain Domain 1 01 1CB10 1 11 Figure 3-4. Level One Descriptors The two least significant bits indicate the descriptor type Table 3-2. Interpreting Level One Descriptor Bits [1:0] Value 00 01 10 11 Meaning Invalid Coarse page table Section Fine page table Notes Generates a section translation fault. Indicates that this is a coarse page table descriptor. Indicates that this is a section descriptor. Indicates that this is a fine page table descriptor. 3-8 ARM920T PROCESSOR MMU SECTION DESCRIPTOR Bits 3:2 (C & B) indicate whether the area of memory mapped by this section is treated as write-back cacheable, write-through cacheable, non-cached buffered or non-cached non-buffered. Bit 4 should be written to 1 for backward compatibility. Bits 8:5 specify one of the 16 possible domains (held in the domain access control registers) that contain the primary access controls. Bit 9 is always written as 0. Bits 11:10 (AP) specify the access permissions for this section. Bits 19:12 are always written as 0. Bits 31:20 form the corresponding bits of the physical address for a section. COARSE PAGE TABLE DESCRIPTOR Bits 3:2 are always written as 0. Bit 4 is always written as 1. Bits 8:5 specify one of the 16 possible domains (held in the Domain access control registers) that contain the primary access controls. Bit 9 is always written as 0. Bits 31:10 form the base for referencing the level two descriptor. (The coarse page table index for the entry is derived from the modified virtual address.) If a coarse page table descriptor is returned from the level one fetch, a level two fetch is initiated. FINE PAGE TABLE DESCRIPTOR Bits 3:2 are always written as 0. Bit 4 is always written as 1. Bits 8:5 specify one of the 16 possible domains (held in the domain access control registers) that contain the primary access controls. Bits 11:9 are always written as 0. Bits 31:12 form the base for referencing the level two descriptor. (The fine page table index for the entry is derived from the modified virtual address.) If a fine page table descriptor is returned from the level one fetch, a level two fetch is initiated. 3-9 MMU ARM920T PROCESSOR TRANSLATING SECTION REFERENCES Figure 3-5 illustrates the complete section translation sequence. Note that access permissions contained in the level one descriptor must be checked before the physical address is generated. 31 Table index 20 19 Section index 0 Translation table base 31 Translation base 12 18 31 Translation base 14 13 Table index 210 00 14 13 0 Section level one descriptor 31 Section base address 20 19 12 11 10 9 8 AP Domain 543210 1CB10 20 12 31 Section base address 20 19 Section index Physical address 0 Figure 3-5. Section Translation 3-10 ARM920T PROCESSOR MMU LEVEL TWO DESCRIPTOR If the level one fetch returns either a coarse page table descriptor or a fine page table descriptor, this provides the base address of the page table to be used. The page table is then accessed and a level two descriptor is returned. This defines either a tiny, a small or a large page descriptor: * * * a tiny page descriptor provides the base address of a 1KB block of memory a small page descriptor provides to the base address of a 4KB block of memory a large page descriptor provides the base address of a 64KB block of memory Coarse page tables have 256 entries, each entry describing 4KB. These entries can provide base addresses for either small or large pages. Large page descriptors must be repeated in 16 consecutive entries. Fine page tables have 1024 entries, each entry describing 1KB. These entries can provide base addresses for either tiny, small or large pages. Small page descriptors must be repeated in 4 consecutive entries and large page descriptors must be repeated in 64 consecutive entries. The figure below shows the format of level one descriptors. 31 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0 00 Fault Large page Small page Tiny page Large page base address Small page base address Tiny page base address ap3 ap3 ap2 ap2 ap1 ap1 ap0 C B 0 1 ap0 C B 1 0 ap CB11 Figure 3-6. Page Table Entry (Level One Descriptor) Bits[1:0] indicate the page size and validity and are interpreted as follows. Table 3-3. Interpreting Page Table Entry Bits 1:0 Value 00 01 10 11 Meaning Invalid Large page Small page Tiny page Notes Generates a page translation fault. Indicates that this is a 64KB page. Indicates that this is a 4KB page. Indicates that this is a 1KB page. 3-11 MMU ARM920T PROCESSOR Bit 3:2 (C & B) indicate whether the area of memory mapped by this page is treated as write-back cacheable, write-through cacheable, non cached buffered or non-cached non-buffered. Domain access control on page 3-19 and Fault checking sequence on page 3-21 show how to interpret the access permission (ap) bits. NOTES Tiny pages do not support sub page permissions and therefore only have one set of access permission bits. Bits 31:10 (tiny pages), 31:12 (small pages) or bits 31:16 (large pages) are used to form the corresponding bits of the physical address. TRANSLATING LARGE PAGE REFERENCES Figure 3-7 on page 3-13 illustrates the complete translation sequence for a 64KB large page. As the upper four bits of the page index and low-order four bits of the coarse page table index overlap, each coarse page table entry for a large page must be duplicated 16 times (in consecutive memory locations) in the coarse page table. If a large page descriptor is included in a fine page table the upper six bits of the page index and low-order six bits of the fine page table index overlap, each fine page table entry for a large page must therefore be duplicated 64 times. 3-12 ARM920T PROCESSOR MMU Modified virtual address 31 Table index 12 Translation table base 31 Translation base 14 13 0 20 19 16 15 12 11 Page index 8 0 12 L2 table index 18 31 Translation base 14 13 Table index 210 00 Level one descriptor 31 Coarse page table base address 10 9 8 Domain 543210 1 01 31 Coarse page table base address 10 9 L2 table index 210 00 Level two descriptor 31 Page base address 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0 ap3 ap2 ap1 ap0 C B 0 1 Physical address 31 Page base address 16 15 Page index 0 Figure 3-7. Large Page Translation from a Coarse Page Table 3-13 MMU ARM920T PROCESSOR TRANSLATING SMALL PAGE REFERENCES Figure 3-8 illustrates the complete translation sequence for a 4KB small page. If a small page descriptor is included in a fine page table, the upper two bits of the page index and low-order two bits of the fine page table index overlap. Each fine page table entry for a small page must therefore be duplicated four times. Modified virtual address 31 Table index 12 Translation table base 31 Translation base 14 13 0 20 19 L2 table index 8 12 11 Page index 0 12 18 31 Translation base 14 13 Table index 210 00 Level one descriptor 31 Coarse page table base address 10 9 8 Domain 543210 1 01 31 Coarse page table base address 10 9 L2 table index 210 00 Level two descriptor 31 Page base address 12 11 10 9 8 7 6 5 4 3 2 1 0 ap3 ap2 ap1 ap0 C B 1 0 Physical address 31 Page base address 12 11 Page index 0 Figure 3-8. Small Page Translation from a Coarse Page Table 3-14 ARM920T PROCESSOR MMU TRANSLATING TINY PAGE REFERENCES Figure 3-9 on page 3-16 illustrates the complete translation sequence for a 1KB tiny page. Page translation involves one additional step beyond that of a section translation: the level one descriptor is the fine page table descriptor and this is used to point to the level one descriptor. NOTES The domain specified in the level one description and access permissions specified in the level one description together determine whether the access has permissions to proceed. See section Domain access control on page 3-19) for details. 3-15 MMU ARM920T PROCESSOR Modified virtual address 31 Table index 12 Translation table base 31 Translation base 14 13 0 20 19 L2 table index 10 10 9 Page index 0 10 18 31 Translation base 14 13 Table index 210 00 Level one descriptor 31 Fine page table base address 12 11 98 Domain 543210 1 11 31 Fine page table base address 12 11 L2 table index 210 00 Level two descriptor 31 Page base address 10 9 6543210 ap CB11 Physical address 31 Page base address 10 9 Page index 0 Figure 3-9. Tiny Page Translation from a Fine Page Table 3-16 ARM920T PROCESSOR MMU SUB-PAGES Access permissions can be defined for sub pages of small and large pages. If, during a page walk, a small or large page has a non-identical sub page permission, only the sub page being accessed is written into the TLB. For example, a 16KB (large page) sub page entry will be written into the TLB if the sub page permission differs and a 64KB entry will be put in the TLB if the sub page permissions are identical. When sub page permissions are used and the page entry then needs invalidating, all four sub pages must be invalidated separately. MMU FAULTS AND CPU ABORTS The MMU generates an abort on the following types of faults: * * * * alignment faults (data accesses only) translation faults domain faults permission faults. In addition, an external abort may be raised by the external system as a result of certain types of external data access. Alignment fault checking is enabled by the A-bit in CP15 register 1. Alignment fault checking is not affected by whether or not the MMU is enabled. Translation, domain and permission faults are only generated when the MMU is enabled. The access control mechanisms of the MMU detect the conditions that produce these faults. If a fault is detected as the result of a memory access, the MMU will abort the access and signal the fault condition to the CPU core. The MMU retains status and address information about faults generated by the data accesses in the fault status register and fault address register (see section Fault address and fault status registers on page 3-18). The MMU does not retain status about faults generated by instruction fetches. An access violation for a given memory access inhibits any corresponding external access, with an abort returned to the CPU core. 3-17 MMU ARM920T PROCESSOR FAULT ADDRESS AND FAULT STATUS REGISTERS On a data abort, the MMU places an encoded 4 bit value, FS[3:0], along with the 4-bit encoded domain number, in the Data fault status register (FSR). Similarly, on a prefetch abort, in the Prefetch fault status register, intended for debug purposes only. In addition, the modified virtual address associated with the data abort is latched into the fault address register (FAR). If an access violation simultaneously generates more than one source of abort, they are encoded in the priority given in Table 3-4 . The fault address register is not updated by faults caused by instruction prefetches. FAULT STATUS The remainder of this chapter describes the various access permissions and controls supported by the data MMU and details how these are interpreted to generate faults. Table 3-4. Priority Encoding of Fault Status Source Highest priority Alignment Translation Domain Permission Lowest priority External abort on NCNB access or NCB read. Section Page Section Page Section Page Section Page Status 0b00x1 0b0101 0b0111 0b1001 0b1011 0b1101 0b1111 0b1000 0b1010 Domain invalid invalid valid valid valid valid valid valid valid FAR MVA of access causing abort MVA of access causing abort MVA of access causing abort MVA of access causing abort MVA of access causing abort NOTES: 1. Data FSR only. Alignment faults may write either 0b0001 or 0b0011 into FS[3:0]. Invalid values in domain[3:0] occur because the fault is raised before a valid domain field has been read from a page table descriptor. Any abort masked by the priority encoding may be regenerated by fixing the primary abort and restarting the instruction. NCNB means Non-Cacheable and Non-Bufferable. NCB means Non-Cacheable but Bufferable. 2. Instruction FSR only. The same priority applies as for the Data fault status register, except that alignment faults cannot occur, and external aborts apply only to NC (Non-cacheable) reads. 3-18 ARM920T PROCESSOR MMU DOMAIN ACCESS CONTROL MMU accesses are primarily controlled via domains. There are 16 domains and each has a 2-bit field to define access to it. Two types of user are supported, clients and managers. See Table 3-5. The domains are defined in the domain access control register. Figure 3-10 illustrates how the 32 bits of the register are allocated to define the 16 2-bit domains. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 3-10. Domain Access Control Register Format Table 3-5 defines how the bits within each domain are interpreted to specify the access permissions Table 3-5. Interpreting Access Control Bits in Domain Access Control Register Value 00 01 10 11 Meaning No Access Client Reserved Manager Notes Any access will generate a domain fault. Accesses are checked against the access permission bits in the section or page descriptor. Reserved. Currently behaves like the no access mode. Accesses are not checked against the access permission bits so a permission fault cannot be generated. 3-19 MMU ARM920T PROCESSOR Table 3-6 shows how to interpret the access permission (AP) bits and how their interpretation is dependent upon the S and R bits (control register bits 8 and 9). Table 3-6. Interpreting Access Permission (AP) Bits AP 00 00 00 00 01 10 11 xx S 0 1 0 1 x x x 1 R 0 0 1 1 x x x 1 Supervisor Permissions No access Read only Read only Reserved Read/write Read/write Read/write Reserved No access Read only Read/write Access allowed only in supervisor mode Writes in user mode cause permission fault All access types permitted in both modes. User Permissions No access No access Read only Notes Any access generates a permission fault Supervisor read only permitted Any write generates a permission fault 3-20 ARM920T PROCESSOR MMU FAULT CHECKING SEQUENCE The sequence by which the MMU checks for access faults is different for sections and pages. The sequence for both types of access is shown below. The conditions that generate each of the faults are described on the following pages. Modified virtual address Check address alignment Misaligned Alignment fault Section translation fault Invalid Get level one descriptor Section Page Get page table entry Invalid Page translation fault Page domain fault Section domain fault No access(00) Reserved(10) Check domain status Section Page No access(00) Reserved(10) Client(01) Client(01) Manager(11) Section permission fault Check access permissions Check access permissions Page permission fault Violation Violation Physical address Figure 3-11. Sequence for Checking Faults 3-21 MMU ARM920T PROCESSOR ALIGNMENT FAULT If alignment fault is enabled (A-Bit in CP15 register 1 set), the MMU will generate an alignment fault on any data word access the address of which is not word aligned, or on any halfword access the address of which is not halfword aligned, irrespective of whether the MMU is enabled or not. An alignment fault will not be generated on any instruction fetch, nor on any byte access. NOTES If the access generates an alignment fault, the access sequence will abort without reference to further permission checks. TRANSLATION FAULT There are two types of translation fault, section and page: Section Page A section translation fault is generated if the level one descriptor is marked as invalid. This happens if bits[1:0] of the descriptor are both 0. A page translation fault is generated if the level one descriptor is marked as invalid. This happens if bits[1:0] of the descriptor are both 0. DOMAIN FAULT There are two types of domain fault, section and page. In both cases the level one descriptor holds the 4-bit domain field which selects one of the 16 2-bit domains in the domain access control register. The two bits of the specified domain are then checked for access permissions as detailed in Table 3-6 on page 3-20. In the case of a section, the domain is checked once the level one descriptor is returned and in the case of a page, the domain is checked once the level one descriptor is returned. If the specified access is either no access (00) or reserved (10) then either a section domain fault or page domain fault occurs. 3-22 ARM920T PROCESSOR MMU PERMISSION FAULT If the 2-bit domain field returns 01 (client) then access permissions are checked as follows: Section If the level one descriptor defines a section-mapped access, the AP bits of the descriptor define whether or not the access is allowed according to Table 3-6 on page 3-20. Their interpretation is dependent upon the setting of the S and R bits (control register bits 8 and 9). If the access is not allowed, a section permission fault is generated. If the level one descriptor defines a page-mapped access and the level two descriptor is for a large or small page, four access permission fields (ap3-ap0) are specified, each corresponding to one quarter of the page. Hence, for small pages ap3 is selected by the top 1KB of the page and ap0 is selected by the bottom 1KB of the page. For large pages, ap3 is selected by the top 16KB of the page and ap0 is selected by the bottom 16KB of the page. The selected AP bits are then interpreted in exactly the same way as for a section (see Table 3-6 on page 3-20), the only difference being the fault generated is a page permission fault. If the level one descriptor defines a page-mapped access and the level two descriptor is for a tiny page, the AP bits of the level one descriptor define whether or not the access is allowed in the same way as for a section. The fault generated is a page permission fault. Large page, small page Tiny page 3-23 MMU ARM920T PROCESSOR EXTERNAL ABORTS In addition to the MMU-generated aborts the ARM920T can be externally aborted by the AMBA bus, which may be used to flag an error on an external memory access. However, not all accesses can be aborted in this way and the Bus Interface Unit (BIU) ignores external aborts that can not be handled. The following accesses may be aborted: non-cached reads unbuffered writes read-lock-write sequence, to non-cacheable memory. In the case of a read-lock-write (SWP) sequence in which the read aborts, the write will always be attempted. 3-24 ARM920T PROCESSOR MMU INTERACTION OF THE MMU AND CACHES The MMU is enabled and disabled using bit 0 of the CP15 control register. ENABLING THE MMU To enable the MMU: 1) Program the translation table base and domain access control registers. 2) Program level 1 and level 2 page tables as required. 3) Enable the MMU by setting bit 0 in the control register. Care must be taken if the translated address differs from the untranslated address as several instructions following the enabling of the MMU may have been prefetched with the MMU off (using physical = virtual address - flat translation) and enabling the MMU may be considered as a branch with delayed execution. A similar situation occurs when the MMU is disabled. Consider the following code sequence: MRC ORR MCR p15, 0, R1, c1, C0, 0: Read control rejection R1, #0x1 p15,0,R1,C1, C0,0 ; Enable MMUS Fetch Flat Fetch Flat Fetch Translated The instruction and data caches can be enabled simultaneously with the MMU using a single MCR instruction. DISABLING THE MMU To disable the MMU, clear bit 0 in the control register. The data cache should be disabled prior to, or, at the same time as the MMU is disabled by clearing Bit 2 of the control register. See the paragraph in Enabling the MMU regarding prefetch effects. NOTES If the MMU is enabled, then disabled and subsequently re-enabled the contents of the TLBs will have been preserved. If these are now invalid, the TLBs should be invalidated before the MMU is re-enabled. See Register 8: TLB operations on page 2-18. 3-25 MMU ARM920T PROCESSOR NOTES 3-26 ARM920T PROCESSOR CACHES, WRITE BUFFER APPENDIX 4 CACHES, WRITE BUFFER ABOUT THE CACHES AND WRITE BUFFER The ARM920T includes an instruction cache, a data cache, a write buffer and a Physical Address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. * The ARM920T implements separate 16KB instruction and 16KB data caches. * The caches have the following features: * Virtually-addressed 64-way associative cache. * 8 words per line (32 bytes per line) with one valid bit and two dirty bits per line, allowing half-line write-backs. * Write-through and write-back cache operation (write-back caches are also known as copy back caches), selected per memory region by the C and B bits in the MMU translation tables (for data cache only). * Pseudo-random or round-robin replacement, selectable via RR bit in CP15 register 1. * Low-power CAM-RAM implementation. * Caches independently lockable with granularity of 1/64th of cache, which is 64 words (256 bytes). * For compatibility with Microsoft WindowsCE, and to reduce interrupt latency, the physical address corresponding to each data cache entry is stored in the physical address TAG RAM for use during cache line write-backs, in addition to the virtual address TAG stored in the cache CAMs. This means that the MMU is not involved in cache write-back operations, removing the possibility of TLB misses related to the write-back address. * Cache maintenance operations to provide efficient cleaning of the entire data cache, and to provide efficient cleaning and invalidation of small regions of virtual memory. The latter allows ICache coherency to be efficiently maintained when small code changes occur, for example self-modifying code and changes to exception vectors. The write buffer can hold 16 words of data and four addresses. 4-1 CACHES, WRITE BUFFER ARM920T PROCESSOR INSTRUCTION CACHE The ARM920T includes a 16KB instruction cache. The ICache has 512 lines of 32 bytes (8 words), arranged as a 64-way set-associative cache and uses modified virtual addresses, translated by CP15 register 13 (see Address translation on page 3-4), from the ARM9TDMI core. The ICache implements allocate-on-read-miss. Random or round-robin replacement can be selected under software control via the RR bit (CP15 register 1, bit 14). Random replacement is selected at reset. Instructions can also be locked in the ICache such that they cannot be overwritten by a linefill. This operates with a granularity of 1/64th of the cache, which is 64 words (256 bytes). All instruction accesses are subject to MMU permission and translation checks. Instruction fetches which are aborted by the MMU will not cause linefills or instruction fetches to appear on the ASB. For clarity, the I bit (bit 12 in CP15 register 1) is referred to as the Icr bit throughout the following text. The C bit from the MMU translation table descriptor corresponding to the address being accessed is referred to as Ctt. 4-2 ARM920T PROCESSOR CACHES, WRITE BUFFER INSTRUCTION CACHE ENABLE/DISABLE On reset, the ICache entries are all invalidated and the ICache is disabled. The ICache is enabled by writing 1 to the Icr bit, and disabled by writing 0 to the Icr bit. The ICache is usually used with the MMU enabled, in which case the C bit in the relevant MMU translation table descriptor indicates whether an area of memory is cacheable. If the ICache is enabled with the MMU disabled, all instruction fetches are treated as cacheable. When the ICache is disabled, the cache contents are ignored and all instruction fetches appear on the ASB as separate non-sequential accesses. NOTES ARM920T implements a non-sequential access on the ASB as an A-TRAN cycle followed by an S-TRAN cycle. It does not produce N-TRAN cycles. If the cache is subsequently re-enabled its contents will be unchanged. If the contents are no longer coherent with main memory the ICache should be invalidated prior to being enabled (see Register 7: Cache operations on page 2-15). The MMU and ICache can be enabled simultaneously by writing a 1 to bit 0 and to bit 12 in CP15 register 1 with a single MCR instruction. INSTRUCTION CACHE OPERATION If the ICache is disabled, each instruction fetch results in a separate non-sequential memory access on the ASB, giving very low performance to burst memory such as page mode DRAM or synchronous DRAM. Therefore, the ICache should be enabled as soon as possible after reset. If the ICache is enabled, an ICache lookup is performed for each instruction fetch regardless of the setting of the Ctt bit in the relevant MMU translation table descriptor. If the required instruction is found in the cache, the lookup is called a cache hit. If the required instruction is not found in the cache, the lookup is called a cache miss. If the instruction fetch is a cache hit and Ctt=1 indicating a cacheable region of memory, then the instruction is returned from the cache to the ARM9TDMI CPU core. If it is a cache miss and Ctt=1, then an 8-word linefill will be performed, possibly replacing another entry. The entry to be replaced, (called the victim), is chosen from the entries which are not locked using either a random or round-robin replacement policy. If Ctt=0, indicating a non-cacheable region of memory, then a single non-sequential memory access will appear on the ASB. NOTES If Ctt=0, indicating a non-cacheable region of memory, then the cache lookup should result in a cache miss. The only way that it can result in a cache hit is if software has changed the value of the Ctt bit in the MMU translation table descriptor without invalidating the cache contents. This is a programming error, as the behavior in this case is architecturally unpredictable and varies between implementations. 4-3 CACHES, WRITE BUFFER ARM920T PROCESSOR INSTRUCTION CACHE REPLACEMENT ALGORITHM The ICache and DCache replacement algorithm is selected by the RR bit in the CP15 control register (CP15 register 1, bit 14). Random replacement is selected at reset. Setting the RR bit to 1 selects round-robin replacement. INSTRUCTION CACHE LOCKDOWN Instructions can be locked into the ICache, causing the ICache to guarantee a hit, and providing optimum and predictable execution time. Instructions are locked into the ICache by first ensuring the code to be locked is not already in the cache. This is tested by flushing either the whole ICache or specific lines. A short software routine can then be used to load the instructions into the ICache. The software routine must either be non-cacheable, or already in the ICache, but not in an ICache line which is about to be overwritten. The instructions to be loaded must be from a memory region which is cacheable. The software routine operates by writing to CP15 register 9 to force the replacement counter to a specific ICache line and by using the prefetch ICache line operation available via CP15 register 7 to force the ICache to perform a lookup. This will miss and a linefill will be performed loading the cache line into the entry specified by the replacement counter. Once all the instructions have been loaded, they are then locked by writing to CP15 register 9 to set the replacement counter base to be one higher than the number of locked cache lines. See Data cache lockdown on page 4-9 for a more complete explanation of cache locking. 4-4 ARM920T PROCESSOR CACHES, WRITE BUFFER DATA CACHE AND WRITE BUFFER The ARM920T includes a 16KB data cache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The DCache has 512 lines of 32 bytes (8-words), arranged as a 64-way set-associative cache and uses virtual addresses from the ARM9TDMI CPU core. The write buffer can hold up to 16 words of data and 4 separate addresses. The operation of the data cache and write buffer are intimately connected. The DCache supports write-through (WT) and writeback (WB) memory regions, controlled by the C and B bits in each section and page descriptor within the MMU translation tables. For clarity, these bits are referred to as Ctt and Btt in the following text. For details see Data cache and write buffer operation on page 4-6. Each DCache line has two dirty bits, one for the first 4-words of the line, the other for the last 4-words, and a single virtual TAG address and valid bit for the entire 8-word line. The physical address from which each line was loaded is stored in the PA TAG RAM and is used when writing modified lines back to memory. A linefill always loads a complete 8-word line. When a store hits in the DCache, if the memory region is WB, the associated dirty bit is set marking the appropriate half-line as being modified. If the cache line is replaced due to a linefill, or if the line is the target of a DCache clean operation, the dirty bits are used to decide whether the whole, half, or none of the line is written back to memory. The line is written back to the same physical address from which it was loaded, regardless of any changes to the MMU translation tables. The DCache implements allocate-on-read-miss. Random or round-robin replacement can be selected under software control via the RR bit (CP15 register 1, bit 14). Random replacement is selected at reset. Data can also be locked in the DCache such that it cannot be overwritten by a linefill. This operates with a granularity of 1/64th of the cache, which is 64 words (256 bytes). All data accesses are subject to MMU permission and translation checks. Data accesses which are aborted by the MMU will not cause linefills or data accesses to appear on the ASB. For clarity, the C bit (bit 2 in CP15 register 1) is referred to as the Ccr bit throughout the following text. 4-5 CACHES, WRITE BUFFER ARM920T PROCESSOR DATA CACHE AND WRITE BUFFER ENABLE/DISABLE On reset, all DCache entries are invalidated, the DCache is disabled, and the write buffer contents are discarded. There is no explicit write buffer enable bit implemented in ARM920T. Situations in which the write buffer is used are described below. The DCache is enabled by writing 1 to the Ccr bit, and disabled by writing 0 to the Ccr bit. The DCache must be enabled only when the MMU is enabled. This is because the MMU translation tables define the cache and write buffer configuration for each memory region. When the DCache is disabled the cache contents are ignored and all data accesses appear on the Advanced System Bus as separate non-sequential accesses. If the cache is subsequently re-enabled its contents will be unchanged. Depending on the software system design, the cache may need to be cleaned after it is disabled, and invalidated before it is re-enabled. See Cache coherence on page 4-10. The MMU and DCache can be enabled or disabled simultaneously with a single MCR which changes bit 0 and bit 2 in the control register (CP15 register 1). DATA CACHE AND WRITE BUFFER OPERATION The DCache and write buffer configuration of each memory region is controlled by the C and B bits in each section and page descriptor in the MMU translation tables. For clarity, these bits are referred to as Ctt and Btt in the following text. The configuration is modified by the DCache enable bit in the CP15 control register, which is referred to as Ccr. If the DCache is enabled, a DCache lookup is performed for each data access initiated by the ARM9TDMI CPU core, regardless of the value of the Ctt bit in the relevant MMU translation table descriptor. If the accessed virtual address matches the virtual address of an entry in the cache, the lookup is called a cache hit. If the required address does not match any entry in the cache, the lookup is called a cache miss. In this context a data access means any type of load (read) or store (write) or swap instruction, including LDR, LDRB, LDRH, LDM, LDC, STR, STRB, STRH, STC, SWP and SWPB. To ensure that accesses appear on the ASB in program order, ARM920T will wait for all writes in the write buffer to complete on the ASB before starting any other ASB access. The ARM9TDMI CPU core can continue executing at full speed reading instructions and data from the caches and writing to the DCache and write buffer while buffered writes are being written to memory via the ASB. Table 4-1 describes the DCache and write buffer behavior for each type of memory configuration. Ctt AND Ccr means the bitwise Boolean AND of Ctt with Ccr. 4-6 ARM920T PROCESSOR CACHES, WRITE BUFFER Table 4-1. Data Cache and Write Buffer Configuration Ctt and Ccr 0 (1) Btt 0 Data cache, write buffer and memory access behavior Non-cached, non-buffered (NCNB) Reads and writes are not cached and always perform accesses on the ASB and may be externally aborted. Writes are not buffered. The CPU halts until the write is completed on the ASB. Cache hits should never occur. (2) Non-cached buffered (NCB) Reads and writes are not cached, and always perform accesses on the ASB. Cache hits should never occur. Writes are placed in the write buffer and will appear on the ASB. The CPU continues execution as soon as the write is placed in the write buffer. Reads may be externally aborted. Writes can not be externally aborted. Cached, write-through mode (WT) Reads which hit in the cache will read the data from the cache and do not perform an access on the ASB. Reads which miss in the cache cause a linefill. All writes are placed in the write buffer and will appear on the ASB. The CPU continues execution as soon as the write is placed in the write buffer. Writes which hit in the cache update the cache. Writes cannot be externally aborted. Cached, write-back mode (WB) Reads which hit in the cache will read the data from the cache and do not perform an ASB access. Reads which miss in the cache cause a linefill. Writes which miss in the cache are placed in the write buffer and will appear on the ASB. The CPU continues execution as soon as the write is placed in the write buffer. Writes which hit in the cache update the cache and mark the appropriate half of the cache line as dirty, and do not cause an ASB access. Cache write-backs are buffered. Writes (Cache write-misses and cache write-backs) cannot be externally aborted. 0 1 1 0 1 1 NOTES: 1. The control register C bit (Ccr) being zero disables all lookups in the cache, while the translation table descriptor C bit (Ctt) being zero only stops new data being loaded into the cache. With Ccr = 1 and Ctt = 0 the cache will still be searched on every access to check whether the cache contains an entry for the data. 2. It is an operating system software error if a cache hit occurs when reading from, or writing to, a region of memory marked as NCNB or NCB. The only way this can occur is if the operating system changes the value of the C and B bits in a page table descriptor, while the cache contains data from the area of virtual memory controlled by that descriptor. The cache and memory system behavior resulting from changing the page table descriptor in this way is unpredictable. If the operating system needs to change the C and B bits of a page table descriptor, it must ensure that the caches do not contain any data controlled by that descriptor. In some circumstances, the operating system may need to clean and flush the caches to ensure this. 4-7 CACHES, WRITE BUFFER ARM920T PROCESSOR A linefill performs an 8-word burst read from the ASB and places it as a new entry in the cache, possible replacing another line at the same location within the cache. The location which is replaced (called the victim) is chosen from the entries which are not locked using either a random or round-robin replacement policy. If the cache line being replaced is marked as dirty, indicating that it has been modified and that main memory has not been updated to reflect the change, a cache writeback occurs. Depending on whether one or both halves of the cache line are dirty, the writeback will perform a 4 or 8-word sequential burst write access on the ASB. The writeback data is placed in the write buffer and then the linefill data is read from the ASB. The CPU can the continue while the writeback data is written to memory via the ASB. Load multiple (LDM) instructions accessing NCNB or NCB regions perform sequential bursts on the ASB. Store multiple (STM) instructions accessing NCNB regions also perform sequential bursts on the ASB. The sequential burst will be split into two bursts if it crosses a 1KB boundary. This is because the smallest MMU protection and mapping size is 1KB, so the memory regions on each size of the 1KB boundary may have different properties. This means that no sequential access generated by ARM920T will cross a 1KB boundary, which can be exploited to simplify memory interface design. For example, a simple page mode DRAM controller could perform a pagemode access for each sequential access, provided the DRAM page size is 1KB or larger. See also Cache coherence on page 4-10. DATA CACHE REPLACEMENT ALGORITHM The DCache and ICache replacement algorithm is selected by the RR bit in the CP15 Control register (CP15 register 1, bit 14). Random replacement is selected at reset. Setting the RR bit to 1 selects round-robin replacement. SWAP INSTRUCTIONS Swap instruction (SWP or SWPB) behavior is dependent on whether the memory region is cacheable or noncacheable. Swap instructions to cacheable regions of memory are useful for implementing semaphores or other synchronization primitives in multithreaded uniprocessor software systems. Swap instructions to non-cacheable memory regions are useful for synchronization between two bus masters in a multi-master bus system. This could be two processors, or a processor and a DMA controller. When a swap instruction accesses a cacheable region of memory (WT or WB), the DCache and write buffer behavior will be the same as having a load followed by a store according to the normal rules described. The BLOK pin will not be asserted during the execution of the instruction. It is guaranteed that no interrupt can occur between the load and store portions of the swap. When a swap instruction accesses a non-cacheable (NCB or NCNB) region of memory, the write buffer is drained, and a single word or byte will be read from the ASB. The write portion of the swap will then be treated as non-bufferable, regardless of the value of Btt, and the processor stalled until the write is completed on the ASB. The BLOK pin will be asserted to indicate that the read and write should be treated as an atomic operation on the bus. Like all other data accesses, a swap to a non-cacheable region which hits in the cache indicates a programming error. 4-8 ARM920T PROCESSOR CACHES, WRITE BUFFER DATA CACHE ORGANIZATION The DCache is organized as 8 segments, each containing 64 lines, and each line containing 8-words. The line's position within its segment is a number from 0 to 63 which is called the index. A line in the cache can be uniquely identified by its segment and index. The index is independent of the line's virtual address. The segment is selected by bits [7:5] of the virtual address of the line. Bits [4:2] of the virtual address specify which word within a cache line is accessed. For halfword operations, bit [1] of the virtual address specifies which halfword is accessed within the word. For byte operations, bits [1:0] specify which byte within the word is accessed. Bits [31:8] of the virtual address of the each cache line is called the TAG. The virtual address TAG is stored in the cache along with the 8-words of data, when the line is loaded by a linefill. Cache lookups compare bits [31:8] of the modified virtual address of the access with the stored TAG to determine whether the access is a hit or miss. The cache is therefore said to be virtually addressed. DATA CACHE LOCKDOWN Data can be locked into the DCache causing the DCache to guarantee a hit, and providing optimum and predictable execution time. When no data is locked in the DCache, and a linefill occurs, the replacement algorithm chooses a victim cache line to be replaced by selecting an index in the range (0 to 63). The segment is specified by bits [7:5] of the virtual address of the data access which missed. Data is locked into the DCache by restricting the range of victim numbers produced by the replacement algorithm, so that some cache lines are never selected as victims. The base pointer for the DCache victim generator can be set by writing to CP15 register 9. The replacement algorithm chooses a victim cache line in the range (base to 63), locking in the cache the lines with index in the range (0 to base - 1). Data is loaded and locked into the DCache by first ensuring the data to be locked is not already in the cache. This can be ensured by cleaning and flushing either the whole DCache or specific lines. A short software routine can then be used to load the data into the DCache. The software routine to load the data operates by writing to CP15 register 9 to force the replacement counter to a specific DCache line and then executing a load instruction to perform a cache lookup. This will miss and a linefill will be performed, bringing 8 words of data into the cache line specified by the replacement counter, in the segment specified by bits [7:5] of the modified virtual address accessed by the load. To load further lines into the cache, the software routine can loop performing one load from each line to be loaded. As each line contains 8 words, each loop should add 32 (bytes) to the load address. The software routine needs to move the victim counter to the next index after it has loaded a line into the last available segment with the current index. As there are 8-segments, this will occur after 8-cache lines have been loaded. Once all the data has been loaded, it is locked by writing to CP15 register 9 to move the replacement counter base to be one higher than the highest index of the locked cache lines. The software routine that loads and locks the data in the DCache can be located in a cacheable region of memory providing it does not contain any loads or stores other than the loads which are used to bring the data to be locked into the DCache. The data to be loaded must be from a memory region which is cacheable. 4-9 CACHES, WRITE BUFFER ARM920T PROCESSOR CACHE COHERENCE The ICache and DCache contain copies of information normally held in main memory. If these copies of memory information get out of step with each other because one is updated and the others are not updated, they are said to have become incoherent. If the DCache contains a line which has been modified by a store or swap instruction, and the main memory has not been updated, the cache line is said to be dirty. Clean operations force the cache to write dirty lines back to main memory. On the ARM920T, software is responsible for maintaining coherence between main memory, the ICache and the DCache. Register 7: Cache operations on page 2-15 describes facilities for invalidating the entire ICache or individual ICache lines, and for cleaning or invalidating DCache lines, or for invalidating the entire DCache. To clean the entire DCache efficiently, software should loop though each cache entry using the clean D single entry (using index) operation or the clean and invalidate D entry (using index) operation. This should be performed by a two-level nested loop going though each index value for each segment. See Data cache organization on page 4-9. DCache, ICache, and memory coherence is generally achieved by: * * cleaning the DCache to ensure memory is up to date with all changes invalidating the ICache to ensure that the ICache is forced to re-load instructions from memory. Software can minimize the performance penalties of cleaning and invalidating caches by: * * * Cleaning only small portions of the cache when only a small area of memory needs to be made coherent, for example, when updating an exception vector entry. Invalidating only small portions of the ICache when only a small number of instructions are modified, for example, when updating an exception vector entry. Not invalidating the ICache in situations where it is known that the modified area of memory cannot be in the cache, for example, when mapping a new page into the currently running process. The ICache needs to be made coherent with a changed area of memory after any changes to the instructions which appear at a virtual address, and before the new instructions are executed. Dirty data in the DCache can be pushed out to main memory by cleaning the cache. 4-10 ARM920T PROCESSOR CACHES, WRITE BUFFER Situations which necessitate cache cleaning and invalidating include: * writing instructions to a cacheable area of memory using STR or STM instructions, for example: -- self-modifying code -- JIT compilation -- copying code from another location -- downloading code via the EmbeddedICE JTAG debug features -- updating an exception vector entry. * * * * another bus master, such as a DMA controller, modifying a cacheable area main memory turning the MMU on or off changing the virtual-to-physical mappings in the MMU page tables turning the ICache or DCache on, if its contents are no longer coherent. The DCache should be cleaned, and both caches invalidated, before the cache and write buffer configuration of an area of memory is changed by modifying Ctt or Btt in the MMU translation table descriptor. This is not necessary if it is known that the caches cannot contain any entries from the area of memory whose translation table descriptor is being modified. Changing the process ID in CP15 register 13 does not change the contents of the cache or memory, and does not affect the mapping between cache entries and physical memory locations. It only changes the mapping between ARM9TDMI addresses and cache entries. This means that changing the process ID does not lead to any coherency issues. No cache cleaning or cache invalidation is required when the process ID is changed. At reset the DCache and ICache entries are all invalidated and the DCache and ICache are disabled. The software design also needs to consider that the pipelined design of the ARM9TDMI core means that it fetches three instructions ahead of the current execution point. So, for example, the three instructions following an MCR which invalidates the ICache, will have been read from the ICache before it is invalidated. 4-11 CACHES, WRITE BUFFER ARM920T PROCESSOR CACHE CLEANING WHEN LOCKDOWN IS IN USE The clean D single entry (using index) and clean and invalidate D entry (using index) operations can leave the victim pointer set to the index value used by the operation. In some circumstances, if DCache locking is in use, this could leave the victim pointer in the locked region, leading to locked data being evicted from the cache. The victim pointer can be moved outside the locked region by implementing the cache loop enclosed by the reading and writing of the Base and Victim pointer: MRC p15, 0, Rd, c9, c0, 0 ; Read D Cache Base into Rd Index Clean or Index Clean and Invalidate loops MCR p15, 0, Rd, c9, c0, 0 ; Write D Cache Base and Victim from Rd Clean D single entry (using VA) and clean and invalidate D entry (using VA) operations do not move the victim pointer, so there is no need to reposition the victim pointer after using these operations. IMPLEMENTATION NOTES This section describes the behavior of the ARM920T implementation in areas which are architecturally unpredictable. For portability to other ARM implementations, software should not depend on this behavior. A read from a non-cacheable (NCB or NCNB) region which unexpectedly hits in the cache will still read the required data from the ASB. The contents of the cache will be ignored, and the cache contents will not be modified. This includes the read portion of a swap (SWP or SWPB) instruction. A write to a non-cacheable (NCB or NCNB) region which unexpectedly hits in the cache will update the cache and will still cause an access on the ASB. PHYSICAL ADDRESS TAG RAM The ARM920T implements a PA TAG RAM in order to perform write backs from the data cache. A write back occurs when dirty data that is about to be overwritten by linefill data comes from a memory region that is marked as a write back region. This data is written back to main memory to maintain memory coherency. Dirty data is data that has been modified in the cache, but not updated in main memory. When a line is written into the data cache, the physical address TAG (DPA[31:5]) is written into the PA TAG RAM. If this line comes to be written back to main memory, the PA TAG RAM is indexed into by the data cache and the physical address (WBPA[31:0]) is returned to the AMBA Bus interface so that it can perform the write back. The PA TAG RAM Array for a 16k data cache comprises 8 segments x 64 rows/segment x 26 bits/row. There are two test interfaces to the PA TAG RAM: Debug interface, see Scan chain 4 - debug access to the PA TAG RAM AMBA test interface, see PA TAG RAM test 4-12 ARM920T PROCESSOR CLOCK MODES APPENDIX 5 CLOCK MODES OVERVIEW The ARM920T has two functional clock inputs, BCLK and FCLK. Internally, the ARM920T is clocked by GCLK, which can be seen on the CPCLK output as shown in Figure 5-1. GCLK can be sourced from either BCLK or FCLK depending on the clocking mode, selected using nF bit and iA bit in CP15 register 1 (see Register 1: Control register on page 2-10). The three clocking modes are FastBus, synchronous and asynchronous. The ARM920T is a static design and both clocks can be stopped indefinitely without loss of state. From Figure 51 it can be seen that some of the ARM920T macrocell signals will have timing specified with relation to GCLK, which can be either FCLK or BCLK depending on the clocking mode BCLK CPCLK ARM920T I/O ASB AMBA bus interface GCLK Rest of ARM920T nF, iA FCLK Figure 5-1. ARM920T Clocking 5-1 CLOCK MODES ARM920T PROCESSOR FASTBUS MODE In this mode of operation the BCLK input is the source for GCLK. The FCLK input is ignored. This mode is typically used in systems with high speed memory. SYNCHRONOUS MODE This mode is typically used in systems with low speed memory. In this mode GCLK can be sourced from BCLK and FCLK. BCLK is used to control the AMBA memory interface. FCLK is used to control the internal ARM9TDMI processor core and any cache operations. FCLK must have a higher frequency and must also be an integer multiple of BCLK, with a BCLK transition only when FCLK is HIGH. An example is shown in Figure 5-2. BCLK FCLK Figure 5-2. Synchronous Clocking Mode If the ARM920T performs an external access, for example, a cache linefill, the ARM920T will switch to BCLK to perform the access. The delay when switching from FCLK to BCLK is a minimum of one FCLK phase and a maximum of one BCLK cycle. An example of the clock switching is shown in Figure 5-3 . The delay when switching from BCLK to FCLK is a maximum of one FCLK phase. BCLK FCLK ECLK Figure 5-3. Switching from FCLK to BCLK in Synchronous Mode Care must be taken if BCLK is stopped by the system so that when BCLK is restarted it does not violate any of the above restrictions. 5-2 ARM920T PROCESSOR CLOCK MODES ASYNCHRONOUS MODE This mode is typically used in systems with low speed memory. In this mode of operation GCLK can be sourced from BCLK and FCLK. BCLK is used to control the AMBA memory interface. FCLK is used to control the internal ARM9TDMI processor core and any cache operations. The one restriction is that FCLK must have a higher frequency than BCLK. An example is shown in Figure 5-4. BCLK FCLK Figure 5-4. Asynchronous Clocking Mode If the ARM920T performs an external access, for example, a cache miss or a cache line fill, ARM920T will switch to BCLK to perform the access. The delay when switching from FCLK and BCLK is a minimum of one BCLK cycle, and a maximum of one and a half BCLK cycles. An example of the clock switching is shown in Figure 54 . When switching from BCLK to FCLK the minimum delay is one FCLK cycle and the maximum delay is one and a half FCLK cycles. An example of the clock switching is shown in Figure 5-5. BCLK FCLK ECLK Figure 5-5. Switching from FCLK to BCLK in Asynchronous Mode 5-3 CLOCK MODES ARM920T PROCESSOR NOTES 5-4 S3C SERIES MASK ROM ORDER FORM Product description: Device Number: S3C__________- ___________(write down the ROM code number) Product Order Form: Package Pellet Wafer Package Type: __________ Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line) SEC @ YWW Device Name @ YWW Device Name @ YWW @ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly Delivery Dates and Quantities: Deliverable ROM code Customer sample Risk order Please answer the following questions: See Risk Order Sheet Required Delivery Date - Quantity Not applicable Comments See ROM Selection Form F For what kind of product will you be using this order? New product Replacement of an existing product Upgrade of an existing product Other If you are replacing an existing product, please indicate the former product name ( ) F What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation Mask Charge (US$ / Won): Customer Information: Company Name: Signatures: ____________________________ ___________________ ________________________ (Person placing the order) Telephone number _________________________ __________________________________ (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information: Company Name: Department: Telephone Number: Date: Risk Order Information: Device Number: Package: Intended Application: Product Model Number: S3C________- ________ (write down the ROM code number) Number of Pins: ____________ Package Type: _____________________ ________________________________________________________________ ________________________________________________________________ __________________________ __________________________ Fax: _____________________________ ________________________________________________________________ ________________________________________________________________ Customer Risk Order Agreement: We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. Order Quantity and Delivery Schedule: Risk Order Quantity: Delivery Schedule: Delivery Date (s) Quantity Comments _____________________ PCS Signatures: _______________________________ (Person Placing the Risk Order) _______________________________________ (SEC Sales Representative) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C2410X MASK OPTION SELECTION FORM Device Number: S3C2410X -__________(write down the ROM code number) Attachment (Check one): Diskette PROM Customer Checksum: ________________________________________________________________ Company Name: ________________________________________________________________ Signature (Engineer): ________________________________________________________________ Please answer the following questions: F Application (Product Model ID: _______________________) Audio LCD Databank Industrials Remocon Video Caller ID Home Appliance Other Telecom LCD Game Office Automation Please describe in detail its application ___________________________________________________________________________ (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) |
Price & Availability of S3C2410X
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |